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TPS3820: Operation when /RESET=Low

Yuta Nishie
Genius 3240 points
Part Number: TPS3820
Other Parts Discussed in Thread: TPS3823, TPS3828, , TPS3824

Hi,

The datasheet page 15, 8.3.4 Watchdog Timer (WDI) contains the following information:

”The watchdog timer can be disabled by disconnecting the WDI pin from the system. If the WDI pin detects that it is in a high-impedance state, the TPS3820, TPS3823, TPS3824, or TPS3828 will generate its own WDI pulse to ensure that RESET does not assert.”

I have any question. 

1) Is it correct to understand that if a WDI transition is entered even once when /RESET=Low, /RESET is fixed to Low?

2) If a WDI transition is entered and /RESET=Low, is there a way to be /RESET to High?

3) Is it possible to be /RESET to High by controlling /MR or by entering a WDI transition again?

Best Regards,

Nishie

  • 0
    TI__Genius 12650 points

    Hi Nishie,

    1) Is it correct to understand that if a WDI transition is entered even once when /RESET=Low, /RESET is fixed to Low?

    If this question is pertaining to disabling the Watchdog, the WDI pin needs to be at high impedance for the internal oscillator to activate. If the WDI is not on high impedance and no pulse is entered, the /RESET pin will stay HIGH for the duration of the watchdog timeout then go low for the duration of the Trst. This cycle will continue until a valid pulse is entered or the WDI pin is put on a high impedance state.  

    2) If a WDI transition is entered and /RESET=Low, is there a way to be /RESET to High?

    When /RESET=LOW, watchdog functionality is disabled until /RESET=HIGH. 

    3) Is it possible to be /RESET to High by controlling /MR or by entering a WDI transition again?

    When /RESET=LOW, there is no way to force it back up to HIGH until the de-asserting condition is met.

    For example, if VDD is above Vth but MR is held LOW for 1s, /RESET will stay LOW for 1s + trst. There is no way of making this time shorter, but you can make the /RESET=LOW longer by putting VDD below Vth indefinitely, in which case /RESET will stay LOW regardless of the MR state. 

    WDI is the lowest priority for the /RESET.

    Jesse 

  • 0 in reply to Jesse Villanueva
    Genius 3240 points

    Hi Jesse-san,

    Thank you for your support.

    And I made a mistake in the text of the data sheet I want to quote. The correct text is below.

    "In applications where the input to the WDI pin is active (transitioning high and low) and the TPS3820, TPS3823, TPS3824, or TPS3828 is asserting RESET, RESET is stuck at a logic low after the input voltage returns above VIT–. "

    I have the following question about ”RESET is stuck at a logic low” in this sentence.

    1) Is it correct to understand that if a WDI transition is entered even once when /RESET=Low, /RESET is fixed to Low?

    2) If a WDI transition is entered and /RESET=Low, is there a way to be /RESET to High?

    3) Is it possible to be /RESET to High by controlling /MR or by entering a WDI transition again?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Genius 12650 points

    Hi Nishie-san

    1) Is it correct to understand that if a WDI transition is entered even once when /RESET=Low, /RESET is fixed to Low?

    Yes, Watch functionality if disabled when /RESET=low. 

    2) If a WDI transition is entered and /RESET=Low, is there a way to be /RESET to High?

    No, There is not way to force /RESET=HIGH when /RESET=low

    3) Is it possible to be /RESET to High by controlling /MR or by entering a WDI transition again?

    No, If /RESET is already low, there is no way to force a HIGH.

    Jesse 

  • 0 in reply to Jesse Villanueva
    Genius 3240 points

    Hi Jesse-san,

    Sorry. Let me ask you an additional question.

    4) Is your answer of (2) correct that/RESET does not become High even in the state shown below? In this case, after the WDI transition is input, the state is fixed with WDI=Low or High. Can /RESET is High after td has passed as shown in Figure 7-1 Timing Diagram?

    5) When considering circuits using FETs, is it necessary to pull down with a resistance of 1kohm?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Genius 12650 points

    Nishie-san,

    4) Yes the timing diagram you provided displays the correct behavior of the device. 

    5) The resistor is not necessary if the FET is being used.

    Jesse 

  • 0 in reply to Jesse Villanueva
    Genius 3240 points

    Hi Jesse-san,

    Thank you!

    Jesse Villanueva said:
    4) Yes the timing diagram you provided displays the correct behavior of the device. 

    I understood that the diagram I provided was correct. Am I correct in understanding that tx in this diagram will be ttout + td?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Genius 12650 points

    Nishie,

    No Tx=Td for this case.

    Jesse 

  • 0 in reply to Jesse Villanueva
    Genius 3240 points

    Hi Jesse-san,

    Thank you for your quick reply! It was helpful!

    Best Regards,

    Nishie

  • 0 in reply to Yuta Nishie
    Genius 3240 points

    Hi Jesse-san,

    Sorry. Let me ask you an additional question.

    Jesse Villanueva said:
    No Tx=Td for this case.

    I misread your answer as "No, Tx=Td for this case."

    If No Tx=Td, what is the value of Tx?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Genius 12650 points

    Hi Nishie,

    Sorry, I forgot the coma. It is Tx=Td.

    Jesse