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TPS65987D: Fast Role Swap triggered by UVP or GPIO "FRSwap Input Event"

GerryP
Prodigy 160 points
Part Number: TPS65987D

Hi,

Hi,

I'm trying to trigger a Fast Role Swap from a GPIO that is mapped to "FRSwap Input Event" but when using the Advanced template for the project I can't get the FRS CC low pulse to be generated from the GPIO falling edge, as suggested by the Host Interface TRM document.

If I use the Standard template with basically the same customisation settings, the FRS CC low pulse is triggered correctly by the GPIO mapped to "FRSwap Input Event" but the timing of the PP1 switch is very different when compared to triggering by the Under Voltage Protection event.

I have setup a TPS65987EVM to look into the behaviour of these two methods. I have attached a block diagram of how the EVM is being used and the two customisation projects (with associated scope captures): one based on the Advanced template with the FRS triggered by UVP and one based on the Standard template with the FRS triggered by GPIO driven by the SYS_PWR threshold comparator.

The questions I have are:

(1) In the case of the Advanced based project with the FRS triggered by UVP, when the UVP threshold is reached the iPad VBUS falls rapdily to VSafe5V which is I assume due to the PP1 switch automatically opening? The iPad then seems to source 5V as a result of the FRS CC low pulse as expected. I have mapped a GPIO to the "PP1 Switch Event" to monitor the switch state but this doesn't seem to matched up with the iPad VBUS waveform. Is there any signicant time delay in the GPIO mapped to "PP1 Switch Event"?

(2) For the advanced based project, when I try to trigger the FRS by the GPIO mapped to "FRSwap Input Event" and with the "Fast Role Swap not initiated by UVP", the FRS CC low pulse isn't generated. Do I have incorrect customisation settings that is preventing the generation of the FRS CC pulse?

(3) In the case of the Standard based project with the FRS triggered by "FRSwap Input Event", the iPad VBUS decay follows SYS_PWR exactly as I assume PP1 switch remains closed until VSafe5V is reached at which point it opens, but there is a long delay before it closes again to become a sink, by which time SYS_PWR is well below 5V. Is this the correct timing? It would be better if the timing could be more like the Advanced based project as in question (1).

Any comments on the above questions would be much appreciated.

Regards,

Gerry

TPS65987D iPad FRS UFP std.pjtTPS65987D iPad FRS UFP adv.pjt