As in
TPS55165-Q1: The SPICE model of TPS55165-Q1 (for LTspice)
I have problem due to bootstrap pins. They generate error in my PSPICE simulation. Can someone explain why BST1 and BST2 showed as open(not connected) are tgy internally not connected?
Node N03008 is between BST1 and C9 and node N02989 is between BST2 and C10
The lib in included as global in the simulation settings.
Kind regards