This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS27S100: Start-up behavior when Enable is set

Part Number: TPS27S100

Hi team,

Could you please answer questions below?

Question 1

Question regarding startup when TPS27S100 is ENABLEd

I believe that if you set a current limit value externally, it will clamp to that current value at startup.
In other words, if the current is limited to 2A externally, the rush current downstream immediately after ENABLE will be clamped to 2A. On the other hand, after the operation stabilizes after ENABLE, when the current reaches the current limit value, eFUSE turns OFF.

Question 2 

Are there any regulations regarding the rise time on the output side when eFUSE is turned on?
I would like to know this to check the SOA due to inrush current when there is a FET downstream.

Thank you for your help.

Regards,

Taito Takemura

  • Hi Takemura-san,

    1. If there is a soft short or overcurrent condition, then the current will be clamped to the current limit value, after which the device will rise in temperature until it hits the thermal shutdown temperature, the overcurrent condition is removed, or the device is disabled. If it goes into thermal shutdown, the current limit will be decreased until the device cools below the thermal shutdown hysteresis.

    However, if there is a hard short to ground, the device will turn off within 1us typ, then will increase the output voltage until the current limit is reached. Please see Section 7.3.2 and Figures 36 and 37 in the data sheet for the full explanation and a visual of the behavior.

    2. Please see the dV/dt(on) specification for rise time slew rates.

    Thanks,

    Patrick

  • Hi Patrick,

    Thank you for your answer

    Question 1

    Sorry for r my lack of explanation. This is a question regarding datasheet 8.2.3 section.

    I believe that if you set a current limit value externally, it will clamp to that current value at startup.
    In other words, if the current is limited to 2A externally, the rush current downstream immediately after ENABLE will be clamped to 2A. On the other hand, after the operation stabilizes after ENABLE, when the current reaches the current limit value, eFUSE turns OFF.

    Is the above understanding correct? If I am wrong, it would be helpful if you could point out which part of my understanding is wrong.

    Question 2

    - Is it correct to understand that Vout rises at this slew rate of the datasheet (6.7 Switching Characteristics dV/dt(on) ) even when eFUSE automatically recovers after detecting overcurrent?

    - If the current is clamped, will the current be clamped when inrush current flows even during automatic recovery?

    Thank you for your help.

    Regards,

    Taito Takemura

  • Hi Takemura-san,

    1. The understanding you described is not correct. The current limiting behavior depends on how strong the short is - Figure 36 shows a moderate short/overcurrent (you can see that the current increases to 2A over 8-10us), in which the device immediately limits the current, whereas Figure 37 shows a hard short to ground (the current increases to almost 2A, past the current limit, in under 2us), in which the device immediately turns off the FET, then turns the output on until the current limit is hit. The startup/steady state conditions that the figures detail are just for showing typical conditions during which these types of shorts happen, but a hard short can happen during device startup and the device would turn off the output then current limit, and a moderate short can happen after the device has stabilized and the device would immediately current limit.

    2. That is correct, when the device recovers after an overcurrent condition is removed or the device recovers from thermal shutdown, the subsequent output slew rate is limited to dV/dt(on).

    Yes, the current will always be clamped to ILIM or ILIM(TSD) even during recovery.

    Thanks,

    Patrick