Hi
The customer design with BQ40Z80 with 6 series cells.
The discharge current is 5A. When the CUV protection is triggered after discharge, the discharge MOS will break down, causing a short circuit and invalidating the undervoltage protection. What are the reasons for DMOS breakdown?
Attached the schematic.
Please help check it.
Thanks
Star
Hi Star,
FETs will enter breakdown when there is a large enough VDS comparatively to the current VGS of the FET. Below are the ratings for the DSG pin of the bq40z80 when on and off.
When working with parallel FETs, we would recommend having the gate connections routed together for each pair of CHG and DSG FET with a resistor in series between them.
If this does not alleviate the issue, I believe this thread below can offer more options to help:
Regards,
Anthony Baldino
