TPS7B86-Q1: TPS7B86-Q1_LDO Pspice Model

Hi Shersingh,

I can test the short to battery conditions in the lab when I'm in tomorrow. Is this device used off-battery such that the input voltage is equal to the BAT voltage during these short conditions?

SHERSINGH BHADORIYA said:

Considering above mentioned point Please let know the PG pin state(High/Low) at different voltages when Vin is increased in step of 1V from 0V to 24V.

Is this a separate test than the above mentioned test or an extension of it? ls the BAT voltage constant while VIN is swept or is VIN = VBAT?

Our team does not have the resources to prioritize this model creation at the moment. 

Regards,

Nick

1. It is an extension of it as we need to check for our complete operating voltage range of the system i.e 6V to 24V.

2. Please perform the required test at your end and let know the LDO behavior and PG pin status in all the condition mentioned in the thread above - Awaiting for the test results. 

Hi Shersingh,

I still do not have a complete picture of the tests you are requesting. Can you please address all of the questions in my last comment?

Thanks,

Nick

Hi Nick,

I had already addressed all of the questions in my above comment!! Pl let know if you any query is unaddressed.

Any update on the testing results? 

Are our raised request for testing the LDO behavior is so time consuming as it has been pending since an week.

Could you pl expedite and share the required results.

Shersingh,

Nick Butts said:

Is this device used off-battery such that the input voltage is equal to the BAT voltage during these short conditions?

Nick Butts said:

ls the BAT voltage constant while VIN is swept or is VIN = VBAT?

I need to know the answer to these questions because it is not clear to me whether a short-to-battery in this case means that the VIN of the LDO is equal to the battery voltage. In some applications a short-to-battery is the same as VOUT = VIN, and in some cases the VBAT > VIN so that when there is a short-to-battery condition, VOUT > VIN. 

If a week is too long for support, I advise following up in time intervals that are less than 5 days. 

Regards,

Nick

Hi Nick,

In our case Vin=VBat and we need the results for the LDO behavior and PG pin status when Vout is gets short to Battery voltage which may be in the mentioned range of 6V to 24V. 

Above results can be captured on Vin of 6V,8V,13.5V,18V & 24V. 

Thanks for your support , We were expecting some progress in an week time.

Please check if you can manage one of the resource who can work on development of Pspice model as well with PG pin.

Hi Shersingh,

I am getting this set up on an EVM. I will finish up tomorrow and send you the results. 

SHERSINGH BHADORIYA said:

Thanks for your support , We were expecting some progress in an week time.

If I had all of the information I requested I could have finished this in one day. Next time, please be sure to follow up with the requested information before your time frame has already passed. 

Regards,

Nick

Thanks a lot for your help & support!!

The required condition to be tested was already discussed in detail for 13.5V condition with Umesh who initiated this thread.

I don't know why Umesh did not had a discussion internally in the meantime with you.

Pl check if you can arrange the Pspice model of it with PG pin by managing your resources in upcoming days, that will be really helpful to each of us and other customers as well.

Hi Nick,

Could you please share the readings / graphs of pins Out, FB/NC pin when EN=1 and Vin is increased in step of 0.5V or 1V for the range 6V to 24V.

Please perform the above-mentioned test above 18V as well, please check whether it is leading to any failures to the LDO.

What will be your plan if we need the Pspice Model with PG pin considering the available resources at your end - Can we have any tentative date for it as our end customer need the simulation results as well. 

Thanks a lot for your support!!

Hi Shersingh,

SHERSINGH BHADORIYA said:

Could you please share the readings / graphs of pins Out, FB/NC pin when EN=1

This is a fixed device so I could not probe FB/NC, and EN = 1V does not result in the device being on as the minimum ON state is 2V, so that is what I used. See the results below. 

As I mentioned in the last slide, the PG pin did not seem to be damaged by the 24V that was seen on it, but that does not mean the customer should do it because this was one unit tested at room temperature so there is no guarantee that devices will not be damaged by this and they should still comply with the abs max ratings. 

STB Test Results.pptx

I can talk to my management to see what we can do about the PSPICE model. This will take a lot of effort so I wouldn't expect to have any model to share before August at least. 

Regards,

Nick

Hi Nick,

Thanks for sharing the test results !!!

Please have a discussion with your management and initiate the actions for the required Spice model.

We will be waiting to hear from you regarding the PSpice model progress post your discussion with the management. 

Hi Shersingh,

I discussed this with management and they are of the same opinion in that we do not have the resources to publish a new model right now. It will for sure be a 2H release window. If there is another way we can help to support your customer's needs let us know.

Regards,

Nick

Hi Nick,

I already had a discussion with the customer in past, they are very clear to have the Pspice model for the simulation and ready to wait till Month of Aug as proposed from your end.

So kindly initiate the tasks for the Pspice model accordingly considering its deliverables.

Hi Shersingh,

August is a tentative date. We will do our best to deliver it by then.

Regards,

Nick

Hi Nick,

We have good hopes from TI for their deliveries. 

Could you please share the circuit details which was tested for the range of 6V to 24V? which is not included in the shared presentation.

Hi Shersingh,

Sorry about that, the PG pullup resistor was 10kΩ, C_DELAY = 1uF, and CIN=COUT=2.2uF. 

Regards,

Nick