TPS4811-Q1: TPS4811-Q1

Hi Rakesh,

1) can you show that  with some sketch  in functional block diagram of datasheet for my better understanding for your answer in previous post .

also my second question

2) what is the minimum and maximum overcurrent,shortcircuit threshold detection limit i can do with TPS4811 smart gate driver.

Because i found TPS4811 has good features and i want to use in four applications of my products  which has different overcurrent and shortcircuit limit in different circuit applications.

Example : i have one application which i need overcurrent and  shortcircuit current detection of 100mA and other three are 700mA,1A,7A.

so what is the minimum and max range which i can detect with TPS4811-Q1

third question:

3)What is the accuracy for current sense ,overcurrent and  short-circuit detection for 100mA and 1A current .For both it is same??

Exclude the current sense resister CS+,IWRN,ISCP resistor tolerance.I need only TPS4811 IC internal tolerance for the detection of above currents.

Thanks in advance Rakesh!!

Hello Rakesh,

Any update on the requested above questions.

Kindly Can you give the faster reply.

Hi Rakesh,

In the design calculation tool it is recommended to set 20% tolerance for IWRN overcurrent protection threshold.Again 20% to the short circuit protection threshold.

Is it really required for the design consideration or can i consider both OCP and SCP the same threshold

for example my max worst case load current is 0.8A and i need OCP and SCP at 0.86A. so can i consider both OCP and SCP same value or any limitation is there ??

Hi Karthik,

I need to check with the design team on this. I can get update by end of this week.

Best Regards,

Rakesh

Hello Rakesh,

Thanks for the reply and due to voltage constraints we are going with TPS48110 and not LM76202.we ordered EVM to perform some tests for OCP and SCP.

Yes, Min OCP is determined by Rsns resistor and Vsns_wrn (10mV to 200mV). if we consider 200mv the power loss in Rsns resitor will be high.

We are using TPS48110  for 0.8A OCP and 0.85A SCP in our application and there could be no problem we are expecting.We will check this after getting EVM board.

 Pending Query:

Q) In the design calculation tool it is recommended to set 20% tolerance for IWRN overcurrent protection threshold with the max load current .Again 20% to the short circuit protection threshold from OCP threshold.

Is it really required for the design consideration or can i consider both OCP and SCP the same threshold??

Kindly as discussed previously  you can check with design team above query and give me reply before end of this week.

Thanks,

Karthik

Hello Rakesh,

Yeah that is clear for me the margin between and OCP and max load current due to Vsns_wrn accuracy which i kept ( for my max load current of 0.7A i considered 0.85A OCP trip threshold which is +20% tolerance .

But my question is can i keep OCP and SCP trip threshold same like 0.85A or in design tool it is recommending again to keep 20% tolerance to OCP threshold for SCP trip which i don't want in my application. i dont want margin between OCP and SCP trip.

If i consider Vsns=20mv for both OCP and SCP threshold  in selection of Rsns,RIWRN,RISCP.

So can i keep OCP and SCP same threshold  like 0.85A or do i have any design limitation in TPS48110 smart gate driver not to keep OCP and SCP .

Thanks in advance rakesh

yes, you can keep OCP and SCP at same level

Hello Rakesh,

Thankyou.

If any further queries during design validation process will connect with you for TPS48110.

Also just wanted to ask one recommendation:

We need low side smart gate driver or smart switch for other application which should be Automotive qualified, operating voltage range 80V and should have Overcurrent OCP,SCP protection for 0.5A and also overvoltage protection.

 Kindly Let me know if any suitable component available in TI.

Thanks,

Karthik

Hello Rakesh,

Maximum load current in my application is 3.75A .

I have considered VSNS_WRN =30.6 which has +/-3% accuracy.

I have set 4A as OCP(Overcurrent protection) threshold and calculated Rsns and RIWRN

Considering Vsns tolerance from datasheet and 1% tolerance of the calculated  RSNS resistor as shown in the below table.OCP thershold i got in the Range of (Min=3.83A,TYP=4A,MAX=4.15A)

For my Maximum load current of 3.75A the OCP threshold range is (min3.83A,TYP=4A,MAX=4.15A) which doesn't have any overlap between Maximum load current and OCP range

I have not considered design tool sheet recommendation of 20% tolerance to max load current and OCP threshold because i am not allowed to give that much tolerance to OCP threshold in my application.

Is there any design limitation still there i can face problem with above mentioned values of  max  load current and OCP threshold??

(Or)  it will be ok until unless there is no overlap between max load current and OCP threshold.

Can you please check and confirm this Rakesh!!

Thanks in advance Rakesh!!!

Hello Rakesh,

First question:

ok ,but considering VSNS_WRN =30.6mV with +/-3% accuracy and Rsns resistor   1% tolerance is it sufficient to determine OCP threshold range (min3.83A,TYP=4A,MAX=4.15A,see above post for details) because there are two  formulas in the datasheet as mentioned below.

I know second formula in the picture is to calculate RIWRN.So the tolerance of RIWRN and RSET resistor also effect the OCP threshold range know??

After  calculating by RIWRN,  if  i consider second formula for calculation of  OCP threshold range, in that VSNS is not there in the formula.I know that Rsns is derived from Vsns-wrn.So considering that i can  take only only Vsns= 30.6mV but not the range of Vsns(29.2 to 31.5mv) which is +/-3% accuracy .

second formula will consider only Rsns,RSET and RIWRN resistors tolerance but not the range of Vsns which is 29.2 to 31.5mv) which is +/-3% accuracy .

So  can you please  help me how i can consider Vsns,Rsns,RSET and RIWRN all tolerance to calculate accurate OCP threshold range???

Second question:

I order to avoid the confusion of  manual calculation ,i tried to go with design tool excel recommended(TI).

By considering 9% tolerance, i set 4.06A as OCP threshold point in order not have overlap with my application maximum load current which is 3.75A.

Again in the design tool it is requested to consider 6.7% tolerance to the OCP threshold point which is show in picture below:

Formula given for total tolerance=SQRT((6.6/100)^2+F25^2+F22^2) ---> what is that 6.6 fixed value considered. Because if i can reduce it in my application i can reduce OCP threshold range or it is compulsory to consider according to design recommendation ???

considering 6.7% tolerance i got OCP range ( 3.78 to 4.33A) as shown below:

 But if consider only  RSNS,RSET,RIWRN  resistors 1% tolerance as show in picture below:

I will get OCP threshold  range (3.95 to 4.19A) which is less than 6.7% recommended tolerance .So what is that 6.6 fixed value in that 6.7% tolerance??.If it is not compulsory to consider i will reduce to 2 to 3% or i will consider range as mentioned above.

Attaching file also your reference

TPS4811-Q1_26th.xlsm

Why i am asking that much particular means Rakesh,OCP is very critical for us and the current  range is more means previous supply block in product will get failed  

Rakesh, Requesting you please check the above query and clarify it to me.

Third Question:

One more question in INRUSH current slew rate control :

Why R1 resistor is recommended to be 100kohms??

If i keep R1 =50kohms it will affect my chargepump (12V, 100uA) or bootstrap capacitor supply ??  any limitation with it??

Thanks in advance Rakesh !!!

Hello Rakesh,

Thank you but in second question answer you  said 6.6 which is  +/-3.3 accuracy. but doubt is why i have to sum-up 3.3+3.3=6.6% accuracy or  3+3=6% accuracy.

Already i have final OCP set point of 4.06A shown below in picture. i have to take  +3%  accuracy to 4.06A which gives Maximum OCP=4.18A and 

-3%  accuracy to 4.06A to get minimum value which is Min OCP=3.938A 

(Min OCP  =3.93A,MAX OCP=4.18A) which does'nt overlap with my maximum operating load current of 3.75A

That could be fine right..summing up of 3+3 =6 % tolerance is  not necessary i think so.

If above my answer is fine means, i will take total  +4%  accuracy(1% for Rsns )  to final OCP set point which get MAX OCP threshold

and same -4%  accuracy to final OCP set point which get Min OCP threshold.

Let me know your comment on it, if it is ok i will proceed Rakesh

Thanks,

Karthik

Hello Rakesh,

Thanks for confirming it,some more questions on SCP and OCP Latchoff time.

First question:

For SCP setpoint of 4A ,i cannot reduce less than +/-13.4% tolerance due to SCP  input bias current itself has 13.3% tolerance as mentioned in electrical characterstics of the datasheet right?--just confirm this rakesh or can we reduce the tolerance  less that 13.4 by any change ?? just asking because as i see large variation of Min and Max range of SCP from typical setpoint i.e (Min=3.8A ,TPY=4.3A,MAX=5A) which is high variation for my application. 

Second question:

OCP CTMR latchoff time

In the TI design tool minimum CTMR considered is 1nF.kepping below that throwing error. So the minimum CTMR is 1nF and  minimum Toc we can achieve is 17us ? ? - please check and Confirm this Rakesh

Third question:

In the TI design tool only OCP with autoretry formula used to calculate CTMR.But my application requirement is OCP with Latchoff.so i considered below formula to calculate CTMR and Toc-overcurrent protection time

Considering CTMR=1nF and i calculated ,

I got ( Min=12.4us,Typ=15.8us,max= 20.17us )This is minimum OCP Toc latchoff time i can achieve??- Please confirm this rakesh

or i can still reduce the CTMR capacitor to lower value like 4.7pF to reduce Toc.

If i consider CTMR=4.7pF,

I got typical Toc latchoff time is Toc=0.074us, 0.074usec is really achievable or we can reduce CTMR< 1nF - Please confirm this Rakesh. 

Fourth question:

In datasheet  for OCP autoretry mode, it is mentioned Toc< 6us for no CTMR connected,this is applicable only for autoretry mode (or) for OCP with LATCH-OFF also ??

Can i keep TMR pin floating with no CTMR and no 100kohm resistor connected for LATCH-OFF mode also , to achieve Toc time< 6us  (or) this is applicable only for Autoretry mode ?? -Please check and confirm this Rakesh 

Kindly please answer above questions for better understanding,

Thanks in advance Rakesh!!

Hello Rakesh,

Thanks for answering above questions!!

1) I will be using Latch-off mode only in my application. So by keeping 100k resistor across TMR pin  with no CTMR capacitor i can achieve  Toc time (<6us)  i.e after reaching OCP setpoint threshold ,(PU pin -FET Vgs) will goes low in <6us time and will be Latched -OFF with no auto-retry-Please confirm this Rakesh

2)Also if i want to use CTMR capacitor  means ,least  value of CTMR capacitor  i can keep is 1nF ???

With 1nF CTMR we can get Toc time16us which the minimum we can acheive with CTMR capacitor-Please confirm this Rakesh.

Thanks,

Karthik.

yes Karthik.. correct

Ok ,thank you Rakesh.

In the datasheet  tolerance is given only for  V(SNS_WRN) 30.6mV and 10mV.

But i will be using  VSNS_WRN =33.42mV due to current sensor resistor available for us.

 could you please check and tell me what is the tolerance for VSNS_WRN =33.42mV

Hi Rakesh,

ok,thank you.

some more questions on inrush current.

question 1:

i am doing tps48110 EVM testing and  I set OCP threshold =3.5A . 

Now we kept capacitive load of 105uf  to check inrush current control of our application requirement and by using the design tool we calculated 

INRUSH current =2.67A which is less than my OCP threshold of 3.5A.

According to the recommendation i kept R1=100kohms and C1=3.3nF for gate of the MOSFET .According to the calculation it should turn-on for 1.1ms with inrush current of 2.6A approxmately.

But you can see below waveform,we are facing an issue . 

INRUSH current it is taking of  5.6A and OCP fault is triggered and you can see output is not even raising to 28V for 1.1ms. Just at 4V it is taking 5.6A and going to fault mode

Kindly Can you check and let me know the issue??

question 2:

Now we checked for 40uF capacitor load ,we did'nt changed the R1=100kohms and C1=3.3nF for gate of the MOSFET and set Tcharge time of 1.1ms only

but according to design tool calculation the inrush curent should be =1A.But we are observing 3.34A current  as seen in below waveform.

Kindly Can you check and let me know the issue??

Acutually my application requirement is, we have 120uF capacitive load and we need inrush current of less that 3.5A by providing MOSFET gate turn-on slew rate control of 500us.

We are working on high priority to freeze the design requirements ,Kindly please check and give the suggestions at the earliest.

Thanks in advance!!

Hi Karthik,

The inrush current profile depends on the FET parameters and their non-linearities. The external cap on the gate gives you flexibility to limit the inrush control but there is no closed loop control as such. If peak current is causing a concern we need to increase C1 to meet the requirement.

Let me know if you have any more questions.

BR,

Rakesh

Hello Rakesh,

I am testing TPS48100EVM ..

I kept CLoad =411uF and for  Tcharge time of 4.5ms the required  R1=100kohms,R2=10ohms and C1=12nF  kept for MOSFET gate.

But during testing i am not required turn-on time according to the calculation ,i measured the  R1,C1 values with DMM  and i kept on the board to observe the typical turn-on time ..but not meeting the aproxmate time.\

I am getting 6.6ms for turn-on time  instead of 4.5ms as shown below

In the EVM Ti is using AUS300N08S5N012ATMA1 MOSFET which has Qg =231nC and for 12V Vbst voltage obtained  C=Q/V, Cg= 19nF and 

Ctotal =C1+Cg=31nF.

If i consider  R1=100kohms,R2=10ohms and Ctotal=31nF then the turn-on time =12ms that is also not matching.

You have any idea  Rakesh why the deviation is coming ??

or something i am missing??

Hi Karthik,

The inrush current is a function of V(BST-SRC). When you enable EN=HIGH, the V(BST-SRC) is building up the voltage so the inrush current is lower than the calculated value with V(BST-SRC)=12V in the tool. So, the turn-on time also increases.

Can you make EN=HIGH first and then use INP to enable the output. Then we should see closer result to the design tool values. 

Hi Rakesh,

i know that actaully and  i am doing also same way in the EVM board.I am doing EN=HIGH first and  then INP making high .

Based on that only i am getting above post results  as mentioned getting I am getting 6.6ms for turn-on time  instead of 4.5ms as shown in above post .

Still not understanding what is the isuue??

As i mentioned it is due to Mosfet gate capcitance?? but still it is different if i take that into account..

Let me know ifyou know any opinion or suggestion on it.

ok. you mean CH3 in the below waveform is EN or INP ?

Can you please capture BST voltage instead of VINPUT and share with me.

I don't think Mosfet gate capacitance is playing major role here.

Hello Rakesh,

Yes the lable name is not correct ,i kept  V_EN label name but i captured INP only .

Ok will try to capture the BST  voltage and then we can discuss based on the observation.

Can you please share your ti email id privately to me.So that i can send the test waveforms in the email due  to some compliance rules. 

Hello Rakesh,

I used INRSUH_FET_SOA  Ti excel tool for SOA.

Actually i need SOA derating for Tam=85 degree what is the allowed current.

In the temperature derated SOA  curve (Green line) current is higher than normal curve (red line)? .generally it should be less than that know..

Also i will using for inrsuh current with active slew rate control .So is there option for start load type capacitive ?? in the tool it is showing only constant current or resistive.

I will sharing you to your email id the design calculation with all the iputs feeded for the selected MOSFET.So please check and give your suggestion on it.

Thanks in advance rakesh!!

Sure Karthik.

Hello Rakesh,

Thanks,any update on the requested query?

I will respond on email today.

Best Regards

Rakesh

 Hello Rakesh,

First question:

Could you please check and tell me what is the tolerance for VSNS_WRN =60mV,125mv which is not mentioned in the datasheet??

Second question:

In the EVM board testing , if you observe in EVM schematic RSNS=500uohms and OCP is 5A then VSNS_WRN=2.5mV and in testing it is exactly tripping and good.

It is mentioned in the datasheet we should not use less that 10mv  due to noise issue.But it is tripping exactly .

But after that i changed the RSNS=8.3mohms in the the EVM board which has VSNS=WRN=31mV and OCP trip should  in between (3.8 to 4.3A) according to my calculation in my design.But the trip is happening at 3.6A which is my operating load current 

so at VSNS_WRN=2.5mv or less value  OCP trip accuracy is good??  or at VSNS high value like 50mV or 100mV OCP trip  accuracy is good??