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Original question:

TPS53659: Default Vboot and use case of TI fusion power designer

TPS53659: VR should support SVID IMON telemetry for Memory RAPL Power Budget Management algorithm

RAJ KUMAR
Intellectual 280 points
Part Number: TPS53659
Other Parts Discussed in Thread: TPS53622

Hi,

As I mentioned in my last queries.

We are using TPS53659 and TPS53622 multiphase regulators in our design to power on the Intel Xeon Processor D-1746TER (Idaville).

I don't want to use input current sense circuitry (shunt resistor or DCR) due to space constraints. but Processor requires IMON telemetry (output current monitoring) for RAPL power budget management algorithm.

Can VR still provide the required IMON telemetry if input current circuitry is not added (VIN_CS & PIN_CSNIN) tied together to VIN??

Thank You 

Raj Kumar 

  • 0
    TI__Guru 67110 points

    Hi

    We can not if input current circuitry is not present.

    Regards

    Yihe

  • 0 in reply to yihe
    Intellectual 280 points

    Hi Yihe,

    Thank You for the response.

    If we refer to the VR block diagram as shown below, I don't see any dependency of ACSPn and IIN blocks. How can IMON current still depends upon Input current?

    Thank You

    Raj Kumar

  • 0 in reply to RAJ KUMAR
    TI__Guru 67110 points

    Hi

    But you are referring to the VINCS in your original question.

    Regards

    Yihe 

  • 0 in reply to yihe
    Intellectual 280 points

    Hi Yihe,

    I think my doubt is not clear to you. sorry for the inconvenience.

    I am trying to explain the same doubt again-

    As you know Intel Xeon Processor requires IMON telemetry (output current monitoring) for RAPL power budget management algorithm. If it doesn't get a valid IMON telemetry, then cold power-on sequence will halt.

    And, I am assuming that IMON is the average or per-phase output current of the power stage (MOSFET) which is acquired and sensed by VR (ACSPn pins, connected to IOUT of Mosfet). means the IMON is the output current data (acquired from IOUT pin of MOSFET).

    Now, If processor requires this output current (IMON) only then can I skip the input current sense circuitry on 12V input due to space constraints?

    In other words, Will the Intel Xeon Processor D1746TER  Power ON if I don't connect shunt or DCR input current sense circuit on 12V input? 

    Please let me know if you have anything to ask regarding the same-

    Thank You 

    Raj Kumar

  • 0 in reply to RAJ KUMAR
    TI__Guru 67110 points

    HI

    They are different the IMON average from the power stage is for the output current which is not the same as the IMON on the 12V 

    The IMON on the 12V typical is larger than the output since 12V can be used as input for other powers. 

    Regards

    Yihe 

  • 0 in reply to yihe
    Intellectual 280 points

    Hi Yihe,

    Means if I follow section 5.3.6 of the datasheet as screen shot given below, which states "When input current sensing is not used, the CSPIN and VIN_CSNIN pins should be shorted together and connected to the power input voltage".

    so, if I don't use input current sensing and do tie up the CSPIN and VIN_CSNIN to 12V input directly. there will be no issue in Intel Xeon's power-on sequencing?. It means this sensed or calculated current is not reported to (or required by) Intel Xeon through SVID interface?

    Thank You

    Raj Kumar

  • 0 in reply to RAJ KUMAR
    TI__Guru 67110 points

    Hi

    Yes, your understanding is correct.

    Regards

    Yihe

  • 0 in reply to yihe
    Intellectual 280 points

    Hi Yihe,

    You mean "if I don't use input current sensing and do tie up the CSPIN and VIN_CSNIN to 12V input directly. There will be NO issue in Intel Xeon's power-on sequencing"???

    Thank You 

    Raj Kumar

  • 0 in reply to RAJ KUMAR
    TI__Guru 67110 points

    Hi

    Yes, you are right

    Regards

    Yihe