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Original question:

TPS53659: Pspice Model and Design spreadsheet/ checklist

TPS53659: Default Vboot and use case of TI fusion power designer

RAJ KUMAR
Prodigy 210 points
Part Number: TPS53659
Other Parts Discussed in Thread: TPS53622

Hi,

As I mentioned in my last queries.

We are using TPS53659 and TPS53622 multiphase regulators in our design to power on the Intel Xeon Processor D-1746TER (Idaville).

I have a few doubts, please help me out.

1) As Intel need a default core supply voltage before it asserts any SVID command that is VBOOT voltage (it is usually 1.2V or 1V). Now please tell me what is the default VBOOT of both the regulators?

2) If the default VBOOT voltage is different from the desired Vboot of the processor then will we have to program the voltage regulator before enabling it (AVR_ON)?

3) We have connect the SVID interface of VR with SVID lanes of processor and PMBus interface of VR with PMBus over the processor itself. Do we need to add one Header (connector) for PMBus to connect the Digital Fusion Power Module?

4) If this Fusion Power Module is required to connected, in this case do we need to keep the VR's output in disabled mode (AVR_EN) low?

5) We are using both the channels (A & B). we want to enable/disable both the channel individually on different timing. How BEN_VCCIO can be used as BVR_EN?

Thank You

Raj Kumar

  • 0
    TI__Guru 60100 points

    Hi

     Chanakya will support you but he is OOO today.

    Regards

    Yihe 

  • 0 in reply to yihe
    Prodigy 210 points

    Okay.

    Thank You

    Raj Kumar

  • 0 in reply to RAJ KUMAR
    TI__Intellectual 1120 points

    Hi Raj Kumar,
    1) The default VBOOT Voltage in TPS53659 for channel A is 1.2V and for Channel B is 2.56V. The default VBOOT Voltage in TPS53622 for channel A is 1V and for Channel B is 0.9V
    2) Yes, If the default VBOOT voltage is different from the desired Vboot we have to program the voltage regulator before enabling it. 

    3) Yes, we need the connector so that Fusion Digital Power Designer can directly communicate with voltage regulators without the processor.

    4)  i) Fusion Digital power designer is kind of GUI to write the PMBUS registers and display the telemetry

         ii) There is no need to disable the VR enable to connect Fusion digital power designer

    5) You need to select the multi function pin (pin13 in tps53659) as BVR_EN either from Fusion GUI or write the 12th bit in D0h address of PMBUS as 0(ensure that you are in page 0 while doing this).

    Best Regards,

    Chanakya.

  • 0 in reply to Chanakya Mandela
    Prodigy 210 points

    Hi Chanakya,

    Thank You so much for the detailed response.

    I have doubt on the 4(ii) point-

    4(ii) If I don't disable the VR while programming it through fusion digital power module then the default Vboot (i.e. 2.56V) can damage my sink device (processor expecting 1.8V). please clarify this.

    I have one more doubt regarding the IMON telemetry-

    I don't want to use input current sense circuitry (shunt resistor or DCR) due to space constraints. but Processor requires IMON telemetry (output current monitoring) for RAPL power budget management algorithm.

    Can VR still provide the required IMON telemetry if input current circuitry is not added or (VIN_CS & PIN_CSNIN) tied together to VIN (12V)??

    I am assuming that IMON is the average or per-phase output current of the power stage (MOSFET) which is acquired and sensed by VR (ACSPn pins, connected to IOUT of Mosfet). means the IMON is the output current data (acquired from IOUT pin of MOSFET).

    In other words, Will the Intel Xeon Processor D1746TER  Power ON if I don't connect shunt or DCR input current sense circuit on 12V input? what is the use case of this input current sense circuitry and sensed values?

    Thank You

    Raj Kumar

  • 0 in reply to RAJ KUMAR
    TI__Guru 60100 points

    Hi

    If the default VBOOT does not match your desired output voltage, you shall program it to right output voltage before power on the system.

    for the IMON, it has been addressed in the other post.

    Regards

    Yihe