Hi Expert,
PN: LP876411B4RQKRQ1
As slvaf93a - Scalable PMIC NVM Update Guide mentioned, if the data value of Page 0 register 0x82, ENABLE_DRV_STAT, is not 0x08, then the register CRC for Page 0 and Page 4 must be computed manually and the results written to the PMIC.
Do you have example code or Python script which use for LP8764-Q1 CRC registers 0xf0-0xf3 recalculation?
Thanks,
Stone