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Original question:

UCC21750: UCC21750

UCC21750: PCB Layout guidelines

Raju Baddipadige
Prodigy 200 points
Part Number: UCC21750

Hi,

I recently reviewed the UCC21750 datasheet and noticed a guideline regarding PCB layout that I'd like to clarify. The guideline states:, I have observed that "If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the ground plane on the output side to shield the output signals from the noise generated by the switch node; if the gate driver is used for the high-side switch, which the COM pin is connected to the switch node, ground plane is not recommended" 

While I understand the general idea, I seek further clarity on the reasoning behind not recommending a ground plane for a high-side gate driver. My assumption is that this recommendation stems from concerns about capacitive coupling with other signals. However, I'm uncertain because if  the switch node voltage changes with high dv/dt, and power supply and other signals also experience similar changes as all referenced to the source/ground. Thus, there would seemingly be no charging/discharging of parasitic capacitance. 

Could you please provide additional insight or clarification on this matter?

Thank you for your assistance.

Best Regards,

Raju Baddipadige

  • 0
    TI__Expert 8185 points

    Hi Raju,

    Thanks for your interest with UCC21750.

    Its always recommended to plan ground plane for COM node. In case of high side switch, the COM is connected to switch node, so it was recommended not to plan a common ground plane. 

    However as you have highlighted, its good to plan the ground plan for COM node. Due to high switching noise, it is good to plan kelvin connection between COM plane and  switch node plane - instead of planning one common ground plane for both COM node and Switch node. By separating these 2 nodes as separate planes, it will help to minimize the noise in the high side COM plane. Hope it helps,

    Thanks

    Sasi

  • 0 in reply to Sasikala Thangam
    Prodigy 200 points

    Dear Sasi,

    Thank you for your prompt response.  However, I regret to inform you that my doubts have not yet been fully resolved.

    "However as you have highlighted, its good to plan the ground plan for COM node. Due to high switching noise, it is good to plan kelvin connection between COM plane and  switch node plane - instead of planning one common ground plane for both COM node and Switch node. By separating these 2 nodes as separate planes, it will help to minimize the noise in the high side COM plane" 

    I believe that your above statement is valid for both the high-side and low-side devices in a half-bridge. If traces with high di/dt are not separated, they may interfere with low-frequency traces as there is a significant voltage drop in high di/dt traces during transients. Why is it specifically written for the high-side device? My doubt is, "if the switch node (high-side switch source/emitter) voltage changes with high dv/dt, and power supply and other signals also experience similar changes as all are referenced to the source/ground. Thus, there would seemingly be no charging/discharging of parasitic capacitance"

    Could you kindly provide further insight into this matter? I would greatly appreciate any additional clarification or guidance you can offer on this topic.

    Best Regards,

    Raju Baddipadige

  • 0 in reply to Raju Baddipadige
    TI__Expert 8185 points

    Hi Raju,

    Yes your understanding is right, the power supply and all signals will be moving wrt to COM. So there is no charging/discharging of parasitic capacitance as all are referenced to COM.

    In our test board for HV testing, we do plan ground plane (for COM) for high side driver as well - but connect to switch node through kelvin connection - not as one big power plane.

    Thanks

    Sasi