Hi,
I recently reviewed the UCC21750 datasheet and noticed a guideline regarding PCB layout that I'd like to clarify. The guideline states:, I have observed that "If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the ground plane on the output side to shield the output signals from the noise generated by the switch node; if the gate driver is used for the high-side switch, which the COM pin is connected to the switch node, ground plane is not recommended"
While I understand the general idea, I seek further clarity on the reasoning behind not recommending a ground plane for a high-side gate driver. My assumption is that this recommendation stems from concerns about capacitive coupling with other signals. However, I'm uncertain because if the switch node voltage changes with high dv/dt, and power supply and other signals also experience similar changes as all referenced to the source/ground. Thus, there would seemingly be no charging/discharging of parasitic capacitance.
Could you please provide additional insight or clarification on this matter?
Thank you for your assistance.
Best Regards,
Raju Baddipadige