Other Parts Discussed in Thread: UCD3138, , UCD3138A, UCD3138PFCEVM-026, PMP40586, PMP20978, TIDA-00512
Hi Team,
I am going through UCD3138_LLC_HB firmware. I have few doubts and kindly clarify the same. I have found the below code in main.c.
//Check to see if FAULT2 is pulled high and FAULT0 is pulled low. //If they are go to ROM. if (MiscAnalogRegs.GLBIOREAD.bit.FAULT2_IO_READ && !MiscAnalogRegs.GLBIOREAD.bit.FAULT3_IO_READ) { pmbus_read_write_rom_mode(PMBUS_WRITE); }
Only fault1 is configured as GPIO after the above condition in init_gpio() other all faults pins as it is.
First of all the comments given in the code and actual condition in the code not matching ( Comment say fault2 & fault0 but actual condition is fault2&fault3).
In UCD3138ALLCEVM150, as shown below fault2 (EXT_OVP_DISABLE) is using as output from UCD3138A for driving the FET Q5. The default pin configuration for fault2 as input and fault since we didn't configure this pin before that above condition.
1. The firmware didn't configure fault2 pin direction as output and GPIO pin then how it will be used for driving Q5?
2. How the same fault2 pin state used for checking whether to clear checksum or not? Instead, we can use fault3 (OVLATCH) which can be controlled.
3. ON/OFF given as fault3 that means if the ON/OFF (FAULT3) is high means UCD3138 detects as fault so we need to set this pin always low? If the fault pin set to high means it will generate fast interrupt and disable the PWM?
4. Is there any document which explains the firmware flow of LLC or any other application for UCD3138A as it is not regular c2000 code flow? (Other than training labs and TRM)
Thanks in advance.