Hi,
I wanted to double-check if my understanding about the DCHG and DDSG pins of BQ76952 is correct.
Assumption:
The DCHG/DDSG pins are configured for DCHG/DDSG functionality.
Statement:
Asserted DCHG/DDSG pins confirms that the CHG/DSG FETs are open. However, the CHG/DSG FETs could be either open or closed when the DCHG/DDSG pins are de-asserted.
Is the above statement true? Or do the de-asserted DCHG/DDSG pins always guarantee that the CHG/DSG FETs are closed?
Thank you,
Kyungjae Lee
