Hi,
I am trying to configure the DCHG/DDSG pins for DCHG/DDSG functionality (Active HIGH). I have followed what's described in the documentation but couldn't get it to properly reflect the DCHG/DDSG status. I have configured both pins to 0x02 but they stay de-asserted even when the faults are triggered and the corresponding FETs are disabled (open). (The device is controlling the FETs in fully-autonomous mode.)
Could you share with me some insights?
I have also read through the following FAQ but the example was to configure these pins ACTIVE-LOW so didn't do much help.
[FAQ] BQ76952: Do the DCHG and DDSG signals on the BQ769x2 follow the CHG and DSG FET driver pin states?
Thank you,
Kyungjae Lee