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LM5069: IC damaged after attaching a charged capacitor to Output

Part Number: LM5069


Tool/software:

Hello,
based on a similar setup of my recent post (https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1377231/lm5069-no-latch-off-after-high-overcurrent-load)
i have a question regarding the effects of attaching charged high capacitances to the output side of the LM5069: By coincidence we found out that attaching a large charged Capacitor at the Output while the input is open leads to desctruction of the IC.


Test Setup (see picture below):

  • Input Line is open and at 0V to GND - nothing connected here
  • C_ext (14mF) is charged to 48V and attached to the Output via mechanical switch

When the mechanical switch is closed we see that the LM5069 IC is damaged and the OUT-Pin is burned.  My thoughts about this:

  • When closing the mech. Switch there will be a high inrush current from C_ext to C1 and C2. A current to C1 higher than approx. 100A would result in a Voltage drop of over 0.3V along the shunt resistors, meaning IN and Sense and exceed the max. specs -> if this is true, why is the OUT pin burned? If this is the reason of the failure, do you see any other solution than adding a Back to Back FET in series to Q1 to block reverse currents?
  • Voltage spikes might occur on the Out and IN line due to bouncing of the switch and oscillation between capacities and line inductance (Output to C_ext: approx. 1m lab wire) -> these should be suppressed by D2/D1 and negative voltages swings should be blocked by D3.
  • Attaching a regular power supply with 48V at the Output and switching on does not result in destruction of the IC. So it must have something to do with high voltage transients or inrush currents

Do you have an idea what could result in a short circuit current through the OUT pin?
Unfortunately, i dont have measurements available for this so far and before burning the next sample PCB i need to have an idea where to look at.

  • Hi,

    I am on travel. I will get back on this by early next week

    BR,

    Rakesh

  • Hi,

    For capacitive heavy loads, we need to use back-to-back FET configuration as shown in Figure-1 in https://www.ti.com/lit/an/snva683/snva683.pdf 

    However, I don't expect OUT pint to get damage as there are clamping diodes. Can you redo the test and capture test waveforms for analysis.

    BR,

    Rakesh

  • Hi Rakesh,
    thanks for your reply. Test measurements are quite difficult as the IC is being killed in the process. This is the reason why i'm asking in the first place -> to get some hints where to focus on. If you have any Ideas or measures in mind please post them here. I will try to repeat the test with lower voltages and see if i can capture some useful information without destroying the IC.

  • yes agree the challenge. I expect some abs max violation as the cause for damage, so let's try to capture waveforms by keeping oscilloscope in trigger mode

  • Update: introducing a back-to-back FET has solved the problem as expected.
    The root cause of the failure is still unknown and i will come back to you i have some measurement data available (if i come to it)

    There is also more question regarding the back-to-back FET:
    Is it possible to use a different(and less expensive) FET for reverse blocking as a wide SOA is not required for this? And what is the influence of different gate-threshold values?  Are there application notes available for this question?

    Thank you!

  • Yes, SOA is not important for reverse blocking FET

    There is no dependency on the gate threshold of the external MOSFETs.