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TPSF12C3: Alternative methods to prevent INJ pin saturation in TPSF12C1 and TPSF12C3

Part Number: TPSF12C3

Tool/software:

Hi Experts,

I am looking into the TPSF12C3 active EMI filter. Based on some initial testing, I have been able to achieve good performance. However, one problem that I have run into is the possible INJ pin saturation. I am aware that the recommended method to prevent this is to increase the choke and Y-capacitor sizes on the SMPS side so that the noise is attenuated more before reaching the sense pins. However, this might not always be desirable, or there does not even seem to be any mentions of them anywhere. Therefore, I would like to ask why the two alternative methods mentioned below (whether or not there is any good reason) are not mentioned anywhere and why they should not be used (For example they just do not work).

The first method would be to reduce the noise levels sensed by the sense pins. This could be done by either reducing the sense capacitor capacitance or by adding an extra resistor in series with them. By doing this you should be able to reduce the input voltage to the internal op amp, thus also reducing the op-amp output voltage swing. Based on the little research I have done, at least one of the problems with lowering the capacitance is that it has to be lowered a lot. Therefore, you easily become limited by the minimum capacitance available for the Y-capacitors, which seems to be around 10pF. However, the series resistor method should still work. So I would like to ask, is there any reason why this sort of method should be avoided? For example, have the internal op amp loop stability components been chosen such that capacitance close to the recommended 680pF is required to achieve loop stability?

The second method, and the method I am more interested in, would be to modify the gain network.  I am aware that this network has some internal components that cannot be changed. However, it seems that by increasing the value of Rg, you are easily able to reduce the INJ pin voltage swing. Once again, is there any reason why this shouldn't be done?




The only given method to help with the INJ pin saturation problem is to "increase the VDD supply voltage, the regulator-side CM choke and/or Y-capacitance, and/or the inject capacitance", which is mentioned in the TPSF12C3 FAQ linked below.

[FAQ] TPSF12C1 and TPSF12C3 power-supply filter IC FAQs - Power management forum - Power management - TI E2E support forums

Below are some sources for given guidelines regarding the gain network and sense capacitors


In the quickstart calculator, it is stated that gain network component values should not be substantially modified. (I tried to attach an image of this, but I don't know whether I was successful). The calculator also states that sense capacitors should be between 330pF and 1nF.

In both forum posts linked below, it is stated that the gain network should remain unchanged. The second link also states the recommended 680pF sense capacitor value.

TPSF12C1 switching frequency adjustment - Power management forum - Power management - TI E2E support forums

TPSF12C3-Q1: How do we select CSENSE and CINJ value? - Power management forum - Power management - TI E2E support forums


Please advise

Regards,

Josel

  • Hi Josel,

    For preventing INJ pin saturation problem, yes, we recommend to "increase the VDD supply voltage, the regulator-side CM choke and/or Y-capacitance, and/or the inject capacitance"

    Using First method which you mentioned - what would be the value of series resistance you would have to keep?

    Second method - There is no reason why it shouldn't be done. You can use this method. To reduce the INJ pin voltage swing, you can increase the value of Rg as long as with the components used - the loop is stable - confirm that the gain and phase looks good and that phase doesn't cross -180 degrees.

    Thanks and Regards,