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UCC21750: Gate Driver false UVLO triggering, Ready pin goes low

Fausto Stella
Prodigy 10 points
Other Parts Discussed in Thread: UCC21750

Tool/software:

Dear all,

I am using a UCC21750 gate driver to drive three half-bridge SiC power modules (MSCSM120AM02CT6LIAG).

Unfortunately, during converter modulation, the ready pin goes low, and the modulation is disabled for around 600 µs. According to the datasheet, this is due to an undervoltage event (UVLO). However, I have monitored all the voltages at the pins of my gate driver, and no issues have been detected. There are plenty of ceramic capacitors near the power pin of my gate driver.

Here are some additional details:

-The other pins are in a normal state (i.e., no faults detected), and the driving signals are correct.
-The gate driver is driving a current buffer, so the current at its output is limited.
-The ready pin triggers only when the DC bus voltage of the converter is above 200 V.
-The oddest thing is that I can partially solve the problem (i.e., I can operate the converter with a DC link voltage of 800 V) when I keep the heatsink floating (i.e., not connected to the ground or to CY capacitors).
-The primary side of the gate driver is supplied with +5V, while the secondary side uses a 6W MGJ6D122005DC insulated DC/DC power converter (+20V/-5V).
-The problem appears even when I am operating the converter at a low switching frequency, i.e., 10 kHz.
-I have built a second, identical converter, and it has the same problem.
-Currently, I am testing the inverter with a three-phase inductor insulated from the ground.
-I tried to reduce the dv/dt down to 10 V/ns, but this has only partially mitigated the problem.

I am at a loss for how to solve this issue. I have used this gate driver on multiple projects over the past few years without any problems.
Can you please help me?

Thank you in advance.

  • 0
    TI__Expert 6730 points

    Hello Fausto, 

    Welcome to E2E! In order to better understand the system and help you solve the issue, I have the following questions/comments: 

    • Could you help share the schematic and layout of the gate driver portion? I'm particularly interested in the layout, since you mentioned you didn't see any problem with UCC21750 in the previous projects. 
    • Does this issue happen every time when you run the system? Is this confined to one gate driver location, or happen randomly across the board? 
    • Do you have any recorded waveform when this happens? 
    • Regarding RDY triggering
      • Sometimes we see glitches on the power supply causing RDY to go low, and this is normal behavior. I would suggest using higher bandwidth probe (1GHz ideally) to check both the VCC and VDD supply, and to make sure there are no voltage dip, even momentarily, below the UVLO threshold. 
        • I would also encourage sending over the waveform so I can take a closer look
      • Besides RDY normal triggering, we want to check whether voltage on the other pins exceeded the absmax voltage 
        • Could you try probing OUTH/OUTL, AIN, and DESAT when this happens, with a high bandwidth probe and short ground loop? 
        • If you have any captured waveform, feel free to share them as well
      • To further debug whether system noise caused this issue -
        • Could you try increasing the gate resistance value to further slow down the dV/dt? 
        • Could you try shielding the gate driver completely with copper tape (top+bottom) to see if the situation improves? 
        • I want to look into this direction because you mentioned floating the heat sink solved the problem - so maybe it has something to do with radiated noise. 

    Please let me know of any test result you have. 

    Thank you! 

    VIvian

  • 0 in reply to Vivian Qi
    Prodigy 10 points

    Dear Vivian,

    Thank you for your prompt reply.

    Attached, you will find the schematic. Please don't be alarmed by the large number of additional components; they were added to create an extra current buffer while maintaining the soft turn-off capabilities. The only issue I'm experiencing is with the IC gate driver.

    -The problem occurs every time the DC-link voltage exceeds 200 V and the heatsink is connected to the ground. This happens with all the high-side gate drivers (the low-side gate drivers seem to work fine, though I'm not 100% certain).

    -I don't have any recorded waveforms at the moment, but I can save them next week if needed. Please let me know what specific measurements you require.

    -I measured the voltage at the driver pins using an optocoupled probe (with a limited bandwidth of 40 MHz), ensuring that the system was not perturbed. I will repeat the measurements using single-ended 1 GHz probes. Please note that there are plenty of capacitors near the power pin of the IC gate driver. According to the datasheet, the undervoltage event should last about 10 µs. I haven't checked for overvoltages yet, but I will do so.

    -I measured the OUTH/OUTL and DESAT pins without noticing anything abnormal. I haven't measured AIN yet, but I can do that as well.

    -I have already tried shielding the gate driver (using a copper shield) and increasing the gate resistance. With these adjustments, I was able to reach a DC-link voltage of 270 V before the error occurs.

    -While I agree with your suggestion about the radiated noise, the slow commutation dynamics and the relatively low voltage at which the problem arises make me think there might be a more serious underlying issue.

    -As mentioned, I don't have recorded waveforms yet, but I can capture some if needed.

    Thank you very much for your help.images_driver.pdf driver_xH.pdf

  • 0 in reply to Fausto Stella
    TI__Expert 6730 points

    Hello Fausto, 

    Thank you for your schematic. It does seem like there are plenty of capacitors on the power pins.

    Waveform will be very helpful in this case. Please see my message above on what waveforms I suggest capturing. 

    Radiated noise exist in the system even when there's low bus voltage on the system. It can come from a variety of places: the switching power module, bias supply, power switch di/dt flowing through bus bar, etc. High current path combined with large loop also has the potential of radiating noise, for example the loop between the 30A buffer and the gate, since it only has 0.125Ohm of turn-on resistance and very minimal turn-off resistance. Thus, I would encourage capturing the waveform to get a better understanding. Another thing you can potentially try is to use copper tape to shield the power module as well as the power supply separately, so we can see whether decreased radiated noise from these two potential sources make a difference in gate driver operation. Also, I want to make sure - previously when you mentioned increasing the gate resistance, you meant increasing the output resistance of IXDD630MYI, correct? So it's larger than 0.125 Ohm. 

    Please let me know of any updates - thank you. 

    Vivian