UCC28951-Q1: Isolated gate drivers

Hello,

Your inquiry is under evaluation and I will get back to you shortly.

Regards,

Hello,

Please see my comments below.

1. I migrated to using isolated gate drivers on primary side as I have switched to SiC FETs since I will be moving to higher voltages. Additionally , I'm using isolated gate driver on output side also ( though reinforced is not required ), but for proto I'm using it. UCC21530 PRIMARY side, UCC21520 SECONDARY synchronous side as per my board functionality. Propagation delays should match / cancel out at input and output side. 

2. Additionally I'm not using Shim inductor as of now, as Excel values suggest not to.

> If the leakage inductance of the transformer supplies enough energy you may not need to add a shim inductor (Ls).

>The following link will bring you to an application note that goes through the step by step design process of a PSFB using the UCC28951.  There is a section on how to size Ls if you decide to use it.

https://www.ti.com/lit/pdf/slua560

3. Rsum : 127k, controller is in CCM Mode always. Current sense : 10R, current sense reset resistor: 1.2K ohm. 

4. Output windings in parallel, vout regulated to 13.1V.

Q1. I had trouble going higher voltages due to loop compensation based on values Suggested by excel sheet, so I put a small capacitor ( 1n ) across EA- bottom divider resistor and ground, which helped moved to higher voltages. Maybe layout noise issues or something need to figure out ? Is this ok to add ?

> Are you sure this loop compensation issue?  You claim the design works at lower input voltages and as you increase voltage you lose regulation.

>You might want to study Vout, Comp and CS when the design is in regulation to determine what is causing the design to not regulate at high line.

>Please note that if the duty cycle demanding is < tmin*fsw the converter enter burst mode.  This could look like a small signal instability.

Resistor Rtmin sets burst mode.

Q2. When going higher voltage or when it's tarts to regulate around 140V and higher ... Transformer current starts to shift negative during the positive  edge. For low voltages low load currents it all looks ok, transformer current remains symmetrical across zero crossings. Is it something to do with compensation or duty cycle ? Or is it something different? Please advise.

> The transformer current will change direction based on the voltage applied across the transformer and it should be symmetrical.

> What could cause you issues it the leading edge current spikes.  These should not be there.  The timing of your SR FETs may be off.  Try disabling the SR FETs and using the FET body diodes to see if this goes away.  If it does you will just need to adjust the SR FET timing.  The application note previously referenced gives guidance on how to set the SR FET timing. 

Yellow : transformer primary current 

Blue and green : secondary side FETs

Yellow : transformer primary current 

Green : transformer primary voltage 

Q3: continuing above problem, Additionally transformer voltage drops momentarily and rises again during higher voltages / higher currents as seen in below image. 

> If the controller voltage across the transformer is dropping as the voltage is increasing the UCC28950 is going into over current protection hiccup mode or light load burst mode.

> Section 7.3.14 in the data sheet will describe how over current hiccup mode protection functions.

> Section 7.3.9 explains how light load burst mode works.

Red : transformer primary 

Blue : one of secondary side FETs drain source 

In the trouble shooting process it might be worth while to obtain a working phase shifted full bridge (PSFB) design to evaluate.  You can use this to see how the PSFB should function during normal operation and large signal transients.  You take waveforms from it and compare it to see what your design is doing and/or not doing.  This can help you in the troubleshooting process of your design.

The following link will bring you to a 600 W evaluation module, (UCC27714EVM-551) , users guide using the UCC28950. The UCC28950 is pin for pin compatible to the UCC28951.  The only difference was the UCC28951 was design to operate at duty cycles greater than 90% duty cycle.  You can order this reference design from ti.com.   In the User's guide for the UCC28950-EVM you will find a schematic, layout and bill of material; as well as critical waveforms.  You may find this information useful as well.

https://www.ti.com/lit/ug/sluub02a/sluub02a.pdf

In your waveforms it looks like the converter is entering light load burst mode and/or over current hiccup mode protection do the leading edge current spike in the transformer.  I have the following recommendations.

1. Review your design with application note SLUA560D and excel design tool.

2. Order evaluation module UCC27714EVM-551 for evaluation.

3. Review the user's guide for schematic, layout example and critical waveforms.

4. Check your transformer turns ratio to make sure nominal duty cycle at all input conditions is > tmin*fsw.

5. Check your current sense transformer and current sense resistor to make sure they are setup and selected correctly.

6. Disable SRs to see if the SR timing is causing the leading edge current spike.  This can be removed by properly setting up FET E and F turn on timings.  Application note slua560d will show how to setup the timings.

Regards,

Below are current waveforms. Are these Ok ? 

DELAB, DELCD: 51K, DELEF : 30k

Yellow: transformer primary current 

Pink : transformer primary voltage 

1. Vin :200V, 40A

2. Vin : around 400V, 20A

3. Also with higher input voltages more than 400VDC, SOme kind of short dip is observed during freewheeling ( flat region , pink colour), how to mitigate or avoid this ??

4. Additionally I'm planning to use hall sensor in place of CT, any relevant circuit design available? What are all the design aspects I need to take care of ?? 

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

Hello,

What did you do to change the transformer primary current waveforms?

The primary transformer current still does not look correct for a phase shifted full bridge. 

The following link will bring you to an application that has a figure of what the primary current of the transformer should look like for a PSFB.  Figure  4-1 in this application note shows what the transformer primary current should look like.

https://www.ti.com/lit/an/slua560d/slua560d.pdf

Regards,

This is happening with changing DELAB DELCD DELEF ... AND with increasing voltage I suppose. Can we keep these delay resistance constant for vin from 200V to 600V ? 

As  per my understanding it's difficult to attain with fixed delay approach if Vin keeps varying. Your thoughts and guidance ??

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,