UCC25660: Power management forum

Hi Aditya,

Your query is under review. I will get back to you within today.

Regards

Hemanth

Hi Aditya,

Regarding LLC converter (UCC256601) operating waveforms: I see you have shared the gate drive voltages, ISNS and VFB. Thank you.

VFB doesn't represent the "V_FBreplica" voltage accurately, which (V_FBreplica) is the critical control variable.

Along with V_FBreplica, the LL pin settings decide the burst mode behavior.

V_FBreplica = (I_FB - I_OPTO) x R_FBInternal

I_OPTO can be estimated by measuring the voltage across R220. I_OPTO = V(220) / R220. 

I request you the following.

1. Measure and share the voltage across R220 across the load with the present settings (you shared). This voltage provides insights in to the V_FBreplica as explained above. 

2. Reduce the LL pin set point to 0.5V and observe the following across the load and share.

a. gate drive voltages (HO, LO)

b. ISNS

c. voltage across R220 (for V_FBreplica).

3. May I also understand what is the output voltage range (min to max) in this application?

Regards

Hemanth

Dear Hemanth sir,

Thanks for your valuable feedback,

1. I am sharing the waveform without any changes, just add the waveform across R220 instead of FB pin waveform.

2. I try to reduce the LL pin set point as per the design tool, I tried 0.441 and 0.617 based on the waveforms I am sharing.

3. Can you suggest how to select a compensation resistor and capacitor values (C55 & R148) for opto.

4. This design is for 48v lead acid battery and its minimum voltage is 42v and maximum is 64v.

5. I am sharing transformer and Lr design sheet please review it also .

6. I select Tset option 5 according to minimum switching frequency is that right ?

Sir, can we connect on call as per your convenient time to review design tools and better solutions.

Please find the attached file .

1000 watt borad detail.zip

Hi Aditya,

I will review the details and get back to you with feedback, recommendations on Monday. 

Regards

Hemanth

Hi Aditya,

Thanks for getting back. It needs be done step by step and correctly.

1. Burst mode settings and programming:

My guidance was to set the LL pin voltage (VLLB) to 0.5. I see both the resistor value sets you used do NOT yield to 0.5V at LL pin, rather they still provide around 1V.

Please use R190--> 75kohm, R189 (620kohm = unchanged). This sets the voltage at LL pin (VLLB) to around 0.5V.

Actions:

a. With this (VLLB=~0.5V), please capture three waveforms (LO, ISNS, V(R221)). 

b. I recommend to place C26 (capacitor on FB pin) close to FB and GNDP pins of UCC25660x for improved immunity. (I see lot of noise on the V(R221)).

c. For proper measurement, I recommend following the below:

i. The waveforms need to be captured with a single point ground (for all three voltage probes) on the PCB close to UCC25660x as reference. This helps avoid ground bouncing and measurement errors due to differential ground voltage references from one probe to another.

ii. Use 100mV/div scale, (20MHz) for V(R221) settings on DSO for readability of the signal.

2. Coming to CC and CV regulation loops:

I see one CC+ one CV in an external MCU and also output OVP on external MCU, one more voltage loop/OVP circuit implemented discretely. 

There should be only one loop / circuit working for CV regulation loop, one for OVP. And these two loops shall not interact with each other; that means the voltage threshold set points has to be kept apart. To start with, you may disable all OVP circuits, so that regulation loop alone works.

Can you please explain which one is used for what? 

a. Circuit with U4 is used for OVP or voltage regulation?

b. What is the internal reference used with circuit R53/R54?

c. What is the internal reference used with (battery sense) circuit R49/R52?

Regards

Hemanth

Dear sir,

Thanks for your valuable feedback,

1. Burst Mode Settings and Programming

A. We set the LL pin voltage (VLLB- 0.54), (R189-620Kohm and R190-75Kohm)

B. We add a capacitor value 2.2nF close to FB pin and GND.

C. We use single ground pin for grounding voltage probe.

we cant measure with 100mV/div scale,  V(R220)  due to unwanted noise .so that we check on 200mv /div scale

Result:- Design is still in burst mode up to 10A

Test condition:-

A. Right now we are not using PFC circuit, we have used Chroma power supply to provide 365 DC voltage to the LLC

@(If we are using PFC circuit the result is the same, design  runs up to 11A in burst mode)

B. And we are not even using iso1 opto with mcu, we are just using TL431 with opto is02

Queries :-

why is optocoupler R220 resistance's across voltage  is sinusoidal. Is there any calculation for selecting value of this resistor (R220)?

How to select a compensation resistor and capacitor values (C55 & R148) for opto.?

Please find the attached file of design waveforms and output details

1000 watt board detail with LL vlg 0.54.zip

thanks & regard

Aditya arya

Aditya,

Thanks for sharing the details.

R220 at opto is a resistance that helps measuring the opto current only. It is not a designed parameter. Recommended to keep within 1k-10kohm for practical purposes.

Let us connect over a call to discuss LL, TSET and feedback loop compensation improvements.

Regards
Hemanth

Dear TI Team,

As you know we are trying to develop a 1000 watt EV charger (65v 15A) . 

Hi Aditya,

Your query is under review. I will get back to you by tomorrow.

Regards

Hemanth

Hi Aditya,

If the LLC circuit alone is working fine when powered from DC source explains that there is noise injection from PFC circuit. 

If the circuit operation is degrading when you try to measure something means, there is some noise injection happening through the measurement. It is important that the measurement system shall not introduce noise into the control circuit. Use high frequency co-axial cables instead of direct passive probes with long ground wire and large loop. That picks up noise and especially if the layout is not the best. 

It is important to measure the switching performance and optimize it on given board, before looking for the converter performance.

 I see the schematic. I have some questions. Please confirm which of the discussed recommendations have been implemented and you see performance improvement, which do not have performance improvement, and which were not implemented.

LLC:

1. Measure the VDS and VGS of each power MOSFET and A-K voltage of diode and see the ringing is not present. If there is unacceptable ringing, take steps to dampen it. Increase the gate resistance value or use better snubber circuit. Please share waveforms.

2. Use high frequency co-axial cables instead of direct passive probes with long ground wire and large loop. The large ground loop picks up noise and inject in to circuit especially if the layout is not the best.

3. What are the values of C55, R148, C128 currently being used? Has C55 been changed to 10nF? I see C128 as 470uF, which is very high. It should be in the range of 100pF to 1nF.

4. What are the values of R22, R12 currently being used?

5. What are the values of R9, C4, R21, C14 and CY3 currently being used? It is not clear from schematic.

6. Consider using 2k in place of R220, and consider shorting R220 with 0ohm once the measurement is over.

7. Did you measure the capacitor C19 voltage with isolated differential probe while in LF burst, no-load to see the voltage does not drop. If it drops, consider increase the capacitance up to 3uF (up to 4.7uF ceramic capacitor).

8. If you are using CY3, connect the primary end of it directly the power cap. Connecting it to control circuit ground disturbs the ground reference.

9. Have a local 10uF capacitor close to secondary side circuit for 12V, where it is actually used. Add a ceramic bypass capacitor between R135 and U4 anode close to these components.

PFC:

What is the PFC controller used ? It is not clear from schematic. I am assuming it as UCC28180.

1. Use at lease 1uF capacitor (and 100nF ceramic, if required) at VCC pin close to IC. The schematic shows the VCC value of 104pF only.

2. Measure Q2 VGS and VDS to confirm damped response. If VGS has high ringing, increase gate resistance.

2. Recommend to use additional independent gate resistance from totem pole driver for paralleling two MOSFETs (Q2, Q14).

3. Use snubber if required at Q2 and/or D28.

4. Use appropriate filter at ISENSE pin. That is Use about 200-300ohms series resistance (R203) for filtering.

5. It is not clear from the schematic the value of the inductance used. I expect you to use it appropriately.

Layout:

With the images provided, I couldn't conduct a detailed layout review.

Regards

Hemanth

Dear Hemanth sir,

LLC;

1. Measure the VDS and VGS of each power MOSFET and A-K voltage of diode and see the ringing is not present. If there is unacceptable ringing, take steps to dampen it. Increase the gate resistance value or use better snubber circuit. Please share waveforms.

Reply;- i will share soon all waveforms  vds & vgs of power mosfet , but there is no ringing .

2. Use high frequency co-axial cables instead of direct passive probes with long ground wire and large loop. The large ground loop picks up noise and inject in to circuit especially if the layout is not the best.

Reply ;- we use shortest ground and we use nearest ic's ground to measure all waveforms  

3. What are the values of C55, R148, C128 currently being used? Has C55 been changed to 10nF? I see C128 as 470uF, which is very high. It should be in the range of 100pF to 1nF.

Reply ;- sorry for sharing wrong value schematic , i ll share updated schematic we use C55- 10nf, R148- 33k ohm , C128- 470pf 

4. What are the values of R22, R12 currently being used?

Reply ;- we use R22& R12 -10 ohm 

5. What are the values of R9, C4, R21, C14 and CY3 currently being used? It is not clear from schematic

Reply ;- the values of R9 -100ohm, C4 -220pf, R21 -100ohm, C14  -220pf  and CY3- 2.2nf.

6. Consider using 2k in place of R220, and consider shorting R220 with 0ohm once the measurement is over.

Reply ;- we use already use 510ohm to 10k but there is no benefits , as per your suggestion i will be     check with 0 OHM share the result  soon.

7. Did you measure the capacitor C19 voltage with isolated differential probe while in LF burst, no-load to see the voltage does not drop. If it drops, consider increase the capacitance up to 3uF (up to 4.7uF ceramic capacitor).

Reply ;- we use100nf  to 1uf  but there is no benefits.

8. If you are using CY3, connect the primary end of it directly the power cap. Connecting it to control circuit ground disturbs the ground reference.

Reply;- with cy3 cap and without cy3 cap result is  same , but as per your suggestion we try to connect directly to  power cap .

.

PFC:

What is the PFC controller used ? It is not clear from schematic. I am assuming it as UCC28180.

Reply;- yes we use ucc28180 PFC IC

1. Use at lease 1uF capacitor (and 100nF ceramic, if required) at VCC pin close to IC. The schematic shows the VCC value of 104pF only.

Reply;- sir 104pf= 100nf(10pf*10000) & also we use up to 10uf  also.

2. Measure Q2 VGS and VDS to confirm damped response. If VGS has high ringing, increase gate resistance.

Reply;- i will share soon all waveform vds & vgs of mosfet , but there is no ringing. 

2. Recommend to use additional independent gate resistance from totem pole driver for paralleling two MOSFETs (Q2, Q14).

Reply;- ok we consider your suggestions next version pcb 

3. Use snubber if required at Q2 and/or D28.

4. Use appropriate filter at ISENSE pin. That is Use about 200-300ohms series resistance (R203) for filtering.

Reply;- we tried before  100 ohm but  no benefits now we tried 300 ohm and share soon result 

5. It is not clear from the schematic the value of the inductance used. I expect you to use it appropriately.

Reply;- we use 200uh inductor according WBDesign pfc tool i already share the WBDesign pfc tool 

Layout:

With the images provided, I couldn't conduct a detailed layout review.

Reply;-  I shared also board file for cadence software in previous mail 

T.I BOARD.brd

Please find attached file of updated schematic pfc & llc 

updated llc schematic.pdfupdated pfc schematic.pdf

Regards 

Aditya arya

Hi Aditya,

Thanks for sharing the updates.

1. I will look forward to see the waveforms requested. It is important to design the gate drive speed based on the layout and noise on the board. You would know when you appropriately measure the gate drive signals both at the FET and at the driver and D-S signals close to FET and close to nearest filter capacitor. These measurements need to be done with FULL bandwidth of the probe (500MHz or higher). I would expect the gate drives to be slowed down when you measure these for both the LLC and PFC.

In the meantime - 

2. As mentioned by you, the LLC converter output current is limited, only when the PFC is turned on. That means there is some noise being injected. You need to first identify the source of noise and filter or attenuate it.

3. As earlier mentioned the FB trace area is close to the HV node. It needs to be kept away in the new layout. Until then, cut the copper area close to ISO1 (if unused), which is very close to inductor L7. Try moving the resistor R40 close to LLC controller (along with C129) and use some value in the range of 100ohm -2kohm to  attenuate the noise (with R220 0ohm).

4. The PFC switching currents find large loop area through C60 and C61. Try adding some small HF capacitors on bottom layer to provide a smaller loop area.

5. Add local filter capacitors for switching frequency component at the output of PFC - Q14(S) - D28 (K).

6. The net "D" is the output of flyback transformer which has highly discontinuous currents. The output is not filtered close to the flyback transformer. The net is taken all the way through the LLC and PFC converters. This is a bad routing. Plan to use filtered VCC and only after filtering plan to take it across the board. Plan a primary VCC currents return path with small inductance loop, which I couldn't locate one. 

7. Decouple the capacitor for the totem pole driver of PFC FETs from VCC of PFC controller.

8. Q2, Q4 gate drive return path loop is large. Improve the layout. 

Regards
Hemanth