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TPS546D24A: design review

Part Number: TPS546D24A

Tool/software:

Hi,

I am using the DC-DC converter to power the RFSOC – XCZU47DR core rail, with 0.85 V ± 25 mV at 25 A.

I am trying to keep the footprint to a minimum while still meeting the accuracy demands.

If possible, I would like a review of the schematic and PSpice outputs I’ve combined. A few notes:

Firstly, I would like a second opinion about the transient deviation with respect to RFSOC demands.

I need clarification on the VOSNS and GOSNS pins. I’ve noted datasheet mentioned connecting them to the regulation point in a Kelvin connection to a capacitor. What is the capacitor value/characteristic?

Most of the time, the closest capacitors to the RFSOC are high-frequency decoupling capacitors with low capacitance—will that be good enough?

ive combined the current schematic Pmbus values , pin strapping configration , Pspice result , and rfsoc demands. 

Best regards, 

Tomer.

 

TPS546D24ARVFR.docx

  • Firstly, I would like a second opinion about the transient deviation with respect to RFSOC demands.

    The simulation is showing -16mV to +15mV, well within the +/- 25mV specification you cited.  At 4A/ns transient rate, layout and bypassing of the very-high frequency capacitors in the 2.2-10nF range will be critical to avoid parasitic inductance from producing a >25mV edge during the current transition.

    Also, avoid having capacitors spaced by 10x value in parallel without an intermediate value as this can introduce an inter-capacitance resonance that could also compromise the output voltage with such fast transients.

    I need clarification on the VOSNS and GOSNS pins. I’ve noted datasheet mentioned connecting them to the regulation point in a Kelvin connection to a capacitor. What is the capacitor value/characteristic?

    Most of the time, the closest capacitors to the RFSOC are high-frequency decoupling capacitors with low capacitance—will that be good enough?

    The remote sense point capacitance doesn't need to have specific target parameters.  The high-frequency capacitors near the RFSOC should be fine.

    I will look over the design you shared, but there is also a design tool and schematic review checklist available in the TPS546D24A product folder.

  •  

    Sorry for the delay getting back to you with a review of your schematic and comments.  Have you down loaded the excel design tool from the product folder?  It will provide some useful guidance.

    1) AGND to PGND

    It looks like you are connecting these with two parallel resistors.  While this is ok for the nets, the AGND pin needs to be directly connected to PGND at the exposed pad under the IC using a device mounting side trace the width of the pin-pad.  The AGND pin to PGND pad connection does not tolerate resistors or even vias well.

    If your design tools require resistors for node breaking, connect the AGND pad to PGND and use the resistors to provide a single-point connection between the AGND pin and the other connections to AGND (AVIN bypass and pin programming)  rather than between AGND and PGND

    2) BP1V5 bypass

    While BP1V5 doesn't generally need 2 parallel capacitors, rather than 2 matched capacitors, you will generally find better performance with a 1.0μF and 470 or 330nF capacitor in parallel.  This spreads out their resonance frequencies and provides a lower overall impedance at higher frequencies.

    3) Pin Strapping looks good.

    I would recommend using the excel tool with the specifics of the 330μF and 22μF capacitors to make sure compensation code 28 (ILOOP = 7, VLOOP = 2) will work for you.  With VLOOP = 2, the average current mode control loop will produce an output impedance of about 5.1mΩ, so you'll want to check what frequency the parallel combination of the output capacitors achieves 5.1mΩ of impedance.

    4) PMBus programmed COMPENSATION_CONFIG

    You included a PMBus programmed compensation config setting that is different from the pin programmed selection by MSEL1.  Are you intending to use that PMBus programmed compensation setting? 

    The high VLOOP gain (3.375 versus 2 from pin programming) is decreasing the output impedance and thus the transient from about 25mV to 16mV, while the higher ILOOP setting (8 versus 7 from pin programming) is improving the phase margin.

    If you are updating the COMPENSATION_CONFIG via PMBus and planning to store it to NVM, make sure you also update PIN_DETECT_OVERRIDE to set COMPENSATION_CONFIG to default to NVM rather than pin programming so that the MSEL1 resistor does not revert your changes.

    If you are writing COMPENSATION_CONFIG after power-on, be aware that while the command can be updated while the output is enabled, the actual compensation can not be, so the value will either need to be Stored to NVM and Restored, or written while the output is disabled.

  • Hi Peter thanks for the professional response, 

    layout and bypassing of the very-high frequency capacitors in the 2.2-10nF range will be critical

    do you mean decoupling capacitors? not all of them are here as the smaller values are close to the rfsoc.

    Also, avoid having capacitors spaced by 10x value in parallel

    noted.

    The high-frequency capacitors near the RFSOC should be fine

    I've asked because the pspice model seems to put a 47uF cap.

  • 1) I'll connect the PGND and AGND pads similar to the layout recommendation in the datasheet.

    2) noted

    3) I've used it

    3)+4) I intend to use PmBus to override the pin strapping. (while output is disabled) . ill recheck about MSEL1 

    best regards, 

    Tomer.

  •  

    Glad to have helped.  If this has resolved you issue, please click the "This has resolved my issue" button so we can close out the thread.