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Tool/software:
Dear TI Team,
Here is my schematic.
We have followed the recommendations from the EVM regarding ESD diodes and added some capacitors for reinforcement, but these changes have not yielded any improvements. Based on our testing, when applying ESD contact of 4K 6K, abnormal current issues arise. If the PF function is enabled, the module locks up completely and requires a power-on reset to return to normal operation.
Our testing conditions are very similar to those described in the E2E link below, and we have also modified the circuit according to the suggestions provided in that link.
Could you please confirm if there are any potential improvements or alternative solutions? Thank you very much for your assistance!
Hello,
I think another modification you can make to your design for ESD performance is to minimize the copper for PACK +/- in your layout, and maximize the copper for BAT+/-. Otherwise ESD optimization on a board level can be somewhat tricky as this can vary from board to board depending on the design. My recommendation again would be to follow what I have given above, and to follow the ESD recommendations in the documentation for this device.
Regards,
Robert.
Hi Robert,
Could you please provide your email address?
I'd like to share our layout with you for review and discussion.
Thanks!
Hello,
Please add me as a friend, then you can send me a direct message.
Regards,
Robert.