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UCC2818: UCC2818 Soft Start Behavior

Thien Huynh
Prodigy 70 points
Part Number: UCC2818

Tool/software:

Hi,

I am trying to make sense of the behavior of the UCC2818. I was under the impression that the soft start voltage will control the rate of rise of the bus voltage during start up. However, that does not seems to be the case during testing. The bus voltage rise time is much faster than the soft start which result in a situation where it reaches the OVP threshold and shut down the controller before the soft start finishes as shown in the scope shot below.

Channel 1: VAOUT Voltage

Channel 2: SS Voltage

Channel 3: Inductor Current

Channel 4: Bus Voltage

You can see that the soft start is only around 3.5V when the bus reaches OV threshold. Is this the expected behavior of the UCC2818?

Thank you,

Thien Nhien Huynh

  • +1
    TI__Mastermind 34790 points

    Hello Thien, 

    Certainly it is not expected that the soft-start should result in an over-voltage at power-up.  

    Perhaps it is a misunderstanding of how the soft-start (SS) works in the UCC2818 controller. 
    As described in Section 8.2.2.2 (page 17 in the datasheet), the SS pin voltage controls the rate of rise of the VAOUT voltage.  It does not control the rate of rise of VSENSE (and indirectly Vout).

    Your waveforms show that VAOUT voltage tracks SS voltage exactly until VAOUT clamps at ~5V while Vss continues to rise until it clamps at ~7.5V.

    What is notable is that VAOUT does not fall toward 0V when PFC Vout exceeds its target regulation level, it continues to rise even during the OV condition. 
    This suggest to me that the error-amp control is open-loop somehow.    Fortunately, the OVP sense uses a separate divider network from Vout to catch the OV.

    Please investigate your feedback path to VSENSE and VAOUT pins to ensure closed-loop operation. 

    ( Aside from that, seeing how the actual inductor current rises quite high with relatively low values of VAOUT, I suggest that the normally expected overshoot (but not to OVP) can be minimized by further slowing down the rise of VAOUT, if necessary, with a larger Css value. )

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Prodigy 70 points

    Hi Ulrich,

    So it appears that the FB resistor was damaged resulting in a lower resistance value which forced the regulation bus voltage to a higher value than before. We were playing around with the PKLIM resistor divider before this and it must have damaged the FB resistor since they were close together. 

    The response is now correct after replacing the FB resistor. However, I have another question. It seems that the VAOUT wasn't tracking the SS voltage perfectly as shown in the scope shot. Is this normal for it to do that?

    Best Regards,

    Thien Nhien huynh

  • +1 in reply to Thien Huynh
    TI__Mastermind 34790 points

    Hello Thien, 

    I'm glad that you found the FB problem and solved the OVP. 

    Honestly, I do not know the answer to your new question. 
    From your scope shot, it appears that the controller allows VAOUT to exceed Vss by about 1V after VAOUT > ~2V. 
    I don't know why this happens, but SS does seem to continue to maintain control over VAOUT except with a 1V offset. 

    This behavior is not covered in the datasheet and I suspect that it is an unintended side-effect of the internal SS circuit design.
    Since it has not been a significant issue for TI support over the decades of use of this part, I guess that most customers simply compensate for the offset (if they even noticed it) by increasing Css to slow the rise of VAOUT a bit more.   

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Prodigy 70 points

    I see. Thank you for your help.