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Original question:

UCC21750: RDY pin intermittently tripping

UCC21750: RDY SIGNAL FALSE TRIGGER in a 2L 3-Phase Inverter (25kVA) using SIC

Rodrigo Mauro Moritz
Prodigy 15 points
Part Number: UCC21750

Tool/software:

Hello,
i'm facing a problem using the UCC21750 +UCC15241 in a 2L 3-Phase Inverter (25kVA) using SIC devices PN:C3M0040120K (2 in parallel).
Some important information about the project:
  • Output power = 25kVA.
  • Output Inductor =196uH.
  • Output Voltage = 220-240V (Phase to neutral).
  • Switching frequency: 45kHZ.
  • DC-BUS VOLTAGE = 830V.
  • VDD-COM = 15V.
  • VEE-COM = -4V.
  • VCC-GND = 5V.
About the issue:
When the converter is operation in nominal load or more than 80%, sometimes the RDY(UVLO) signal is trigger, but it seems to be no issue in the supply voltage levels. 
In the waveformas below, it is possible to observer, that the UVLO line is pulled down (green) and the switch command stop to work at the same time (yellow).
In blue and red, is possible to observer the VDD (15V) and the VCC (5V) voltages, that seems to be fine.
This problem only happens, when the deadtime is less than 400ns. With a deadtime of 400ns, this problem is not observed.
It seems to be a noise issue, but i want to know, if there is someone that already face some similar problem.
thank you,
  • 0
    TI__Expert 6670 points

    Hi Rodrigo, 

    Thanks for the above waveforms. The waveforms look extremely noisy, and I wonder if it's caused by system noise coupled into the probe, or the actual waveforms seen on the pins. Can you confirm the probing method and type of probes used? 

    If they are the actual voltages seen on the pins, then I can see clear violations of our specs above the absolute maximum values. For example VCC seems to drop to ~-4V and overshooting to ~10V. I definitely won't say the VCC and VDD waveforms look fine. 

    Also, two observations I have on the waveforms/your description: 

    1. Around 7us before RDY pin falls, the VCC-GND waveform seemed more noisy than the other switching cycles. It's possible that this triggered UVLO in the system. A cleaner waveform can help us understand this more. 
    2. You mentioned the issue going away with >400ns dead time. Looking at the waveforms, seems like it takes ~500ns for the Vgs to rise and fall, although it's hard to see since it's 5us/div minimum. Could be shoot-through causing more stress on the system and impacting the power supplies as well. 

    If you can, I would suggest capturing the VCC/VDD waveforms as close to the pin as possible, using a probe with small ground loop. Thus we can have a clearer picture on whether UVLO triggered. Also, does this issue happen only on one board, or on multiple boards you're testing? 

    Looking forward to your reply, 

    Vivian