UCC28064A: Decrease distortion near zero crossing to improve of the THD

Hello Takahara-san, 

Changing the Rzxx resistor values in (1) and (2) should have no effect, as you have found. 

I thought that maybe improving the VINAC signal at the zero-crossing might help, but you have already tried reducing CIN (5) and reducing the VINAC filter time constant (3), with no improvement of distortion.  Increasing Cinacx (4) will not help, and will probably increase distortion. 

Increasing Rt (6) results in reduced available on-time and also reduced available maximum output power. 
Instead, I suggest to try decreasing the Rt value, but not too much, to avoid allowing too much extra output power.  Maybe to 91kR or 82kR, to allow a little lower frequency and longer on-time near the zero-crossings.  

Another idea to try is to slow down turn-off of the MOSFETs (to extend on-time), maybe by increasing the gate resistors RGx to 10R.

I do think that reducing CIN to 0.1uF may still be an option for you, if conducted-EMI is not significantly degraded.

Please note that increasing the on-time at low-line (115Vac) will also increase on-time at high line (230Vac).
Improvement of distortion at 115V may degrade distortion at 230V.  
You may have to make a compromise to achieve the combined minimum distortion at all input voltages where THDi is evaluated. 

Regards,
Ulrich

Hello Takahara-san, 

Thank you for the waveforms.  They are very helpful. 

I believe that you are losing the ZCD signals at the zero-crossings.  
The input voltage is so low that the ZCD-winding voltage cannot drive the ZCDx signal high enough to exceed the 1.7V arming threshold. 

You can try to decrease the turns-ratio of the ZCD winding (add more turns) to raise the low voltage, but that is a complicated solution (new magnetic design) and may adversely affect the ZCD voltage at the peak of high-line.  Vzcd may not be able to fall to <1.0V to trigger a new switching cycle. 

A simpler solution is to add a pull-up resistor (from VREF) to each ZCDx input to provide a little boost to the ZCD voltage at the zero-crossing to rise above 1.7V.  For example: Adding 240kR from VREF to ZCDx will add about +0.5V offset to the ZCDx voltage when Rzx1+Rzx2 = 22kR.  That can help the ZCD signals to work to lower input voltages near the zero-crossing. 

However, this same offset might hurt the ZCD operation at the peak of high-line where the Vout-Vin(peak) difference voltage is very small. 
the extra offset, might prevent Vzcdx from falling below 1.0V to trigger the next cycle. 
But this may not be a problem if THDi measurement is not important at the highest input line voltage.

try adding the pull-up resistors and experiment with their values 100kR to 1MegR, for example) to find the highest value necessary (minimum offset) to improve your zero-crossing distortion.  

Note: any time that the ZCDx signals cannot cross through the 1.7V arming-threshold (Vzcd rising) or the 1.0V triggering-threshold (Vzcd falling), switching will stop.  In this case, switching will automatically attempt to resume only after a ~210us restart-timer has elapsed.  You can see this time interval in the waveforms.   There is no way to make this timer faster.  The min/max spec on this timer is 160us to 265us, and 210us is typical. 
 
So please be aware: even if you add a pull-up resistor to ZCDx and the offset allows switching closer to 0V, if the switching does stop due to loss of ZCD voltage, there will always be a ~210us interval of no switching until restart timer elapses and forces a GDx pulse to try to restart.  GDA and GDB are driven at the same time by the restart timer, and interleaving resumes after a few consecutive switching cycles. 

Regards,
Ulrich

Hello Takahara-san, 

In your schematic diagram, Rza2 connects to ZCDA which corresponds to GDA connected to Q101. 
In your latest waveforms, I assume that the "V(Rza2-AGND2)" label correctly identifies the ZCDA signal so I think that the MOSFET2 and MOSFET1 waveform labels are mixed up.  The labeling is not so important; it is clear in Figure (a) that Channel-4 Vgs corresponds to the Channel-5 ZCD signal.  

Since Channel 3 MOSFET shutdown but the ZCDB signal is not shown, it is possible that either ZCDB was not able to rise above 1.7V, OR, ZCDB was not able to fall below 1.0V to trigger then next pulse.  My guess is that ZCDB did rise higher than 1.7V (since ZCDA in Channel-5 clearly does), but too much pull-up current (Rpull-up too low) prevented ZCDB from dropping below 1.0V to trigger the next pulse. 

In Figure (b), it can be seen that ZCDA (Channel-5) failed to exceed 1.7V to arm the zero-current detector to be able to detect when demagnetization is finished and trigger the next GDA pulse.  So switching of  Q101 stopped. 

In Figure (c), it can be seen that ZCDA Channel-5 now correctly corresponds to Q101 Vgs on Channel-3.  Although the waveform labeling is the same as in Figure (a), I have to assume that one or more probes were moved between capture of (a) and capture of (c). 
In this Figure, both ZCDA and ZCDB signals met the criteria to trigger sequential gate-drive pulses. 

For both PFC channels (Phase-A and Phase-B), the MOSFET turn on depends on ZCDx signal meeting 2 requirements:
1.  ZCDX voltage during MOSFET off-time (demagnetization of inductor) must rise above 1.7V to "arm" the zero-current detector to look for the inductor's "zero-current" condition.  The ZCD circuit will not look for zero-current until it has been established that there is some current in the inductor in the first place.  This is a difficult condition to meet when the input voltage is near 0V.  The MOSFET on-time has to be very long to build up current in the inductor with only 1~2V across it.  Then, after the MOSFET does turn off, that peak current must be able to charge the switched-node capacitance (mostly Coss, but also diode and other capacitance) up to a voltage high enough that the ZCDx voltage rises by the winding turns-ratio above 1.7V.

Only after this happens, then the ZCD circuit begins to look for the moment when ZCDx signal falls back down below 1.0V.  This is when the peak current in the inductor has demagnetized enough that the inductor voltage starts to decrease.  The turns ratio reflects this decrease and when Vzcdx < 1.0V, it triggers the turn-on MOSFET gate-drive for the next switching cycle. 

It is important to realize that the switching pulses are asynchronous with the AC line, and its input voltage zero-crossing time.
Since continuous switching depends on ZCDx signals always being within spec, there are times when Vzcdx cannot rise > 1.7V, and times when it cannot fall < 1.0V and switching might stop on either or both MOSFETs.  Sometimes you get lucky and both FETs keep switching right through the zero-crossing. 

The random factor here is whether the input voltage is high enough to set up the ZCDx voltages correctly at the right times to keep the switching going.
This randomness is unavoidable, and I think random dead times (MOSFET off) at the zero-crossings are unavoidable.    

A pull-up resistor from VREF to ZCDx can make it easier to reach 1.7V, but at the same time it also makes it harder to fall back below 1.0V.  

At this point, I don't think there is a simple way to improve the input current at the voltage zero-crossing.
Longer on-times might help a little, but the inductance limits how high the peak current can get. 
Lower inductance can help more by allowing higher peak currents at low Vin, but now the switching frequency will increase a lot and several other control parameters will have to change to accommodate this.  

At some point, there will be diminishing returns on the time, effort, and cost spent to develop special circuits to fine-tune the distortion around the AC zero-crossing.  I suggest to reassess whether further reducing the existing current distortion is actually necessary and worth the expense. 

Regards,
Ulrich