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UCC25660: Doesn't start-up.

Part Number: UCC25660

Tool/software:

Hello to all.
I working on a new design ordinary 100W LLC, running at a quite high frequencies. For now I built new prototype based on UCC256601DDBR, working at quite low frequency
Design fed by 380VDC bus.
Input stage with filter, as well as the secondary side, are not shown, but I can attach it on a request, if someone will be interested.

The problem, design doesn't start at all.
No one pulse at the LO pin, which in turn will allow Cboot to be charged.

Here is the list of abnormal behaviour moments, I try to present:

a) no one pulse at the LO pin (capturing with trigger in "single" mode).
b) VCCP pin voltage stays at VccreststartJfet almost all the time, in certain samples, each second, it starts to rise till Vccstartsself (monotonously), then decays back to VccrestartJfet (monotonously). (please see screenshot PIN 12).
c)  V5P in certain cases reaches 5V (immediately or doing some amount of attempts) then stays at 5V. In certain cases, it stands up to 5V, stays some ms then falls down. (please, see attached screenshot PIN8)
d) OVP/OTP pin always 0V(the internal current source doesn't activate), despite there is no short circuit at the pin.

What I have found, Tset divider upper value imposes serious impact on the V5P behaviour, despite specified Vccp 10mA current capability during the start-up.




PIN 8:
PIN 8

PIN 12:
PIN 12


I tried to completely short ISNS pin to the GND, to avoid possible spurious CS protection triggering, but no effect.

I'll would like to ask you to check my design, hint me, what can be wrong.

Please, find complete power stage schematic attached as a PDF
UCC256601DDBR 100W LLC.pdf

  • Hi Alex,

    The HV pin shouldn't be connected to the DC input voltage in case of UCC256601 variant due to X-cap discharge feature. Since the controller doesn't able to detect the zero crossing at the HV pin, X-cap discharge is going to be activated. This would make the IC heat up and trigger Internal OTP. It could be the reason why controller is not starting up.

    Could you also remove the VCC clamp circuit for now as shown below.

    You need to use UCC256602 variant which has HV startup and X-cap discharge disabled.

    For debugging purpose, please follow the below method for starting up with UCC256601 until you get samples of 603 variant.

    1. Depopulate R5 from current board 

    2. Apply VCCP of 16V using an external power supply.

    See whether you are able to see pulses.

    Regards

    Manikanta P

  • Hi Manikanta!
    Thank you so much for so brief going deep in my issue.
    My bad, I missed X-cap discharge section at all, as considered it as a redundant for my design.
    Sure, I'll work out the steps, you provide.
    I'll be back as only will get updates!

  • Manikanta,
    while I'm reworking my PCB accordingly to yours reccomendations.
    Please, advice me, are both functions works together?
    Please, see a pic.1 attached.
    Pic.1
    Seems chip is able to supply VCCP cap with integrated HV current source, and, perform a X-cap discharge function through the same pin.
    Am I right?

    I'm asking it, as I use UCC25660EVM-064 board, with default chip soldered on it, fed by 380VDC, with jumper between points "Vin" and "HV Diode" connected, as specified in the section 2.2 of the user manual.

  • Hi Alex,

    Seems chip is able to supply VCCP cap with integrated HV current source, and, perform a X-cap discharge function through the same pin.
    Am I right?

    Thats correct.

    Section 2.2 is applicable when you use UCC256602. The EVM comes with the UCC256601.

  • Manikanta,
    I disconnected R5, connected 16V external PSU to C7||C8.
    No 5V at V5P.
    Even though, V5P shows some short 1V pulse ~100mS length, when I either
    a) apply 16V
    or
    b) disconnect 16V
    Both cases are shown at the pic.2
    pic.2

    No pulses at LO.
    I'll get __02 samples and update the topic.

    Please, do not close treat.

  • Hi Alex,

    Could you also make following changes when you are testing with 601:

    1. Could you increase each of the TSET resistor values by 10 times (191k and 100k). so that it will reduce the current consumption from V5P.

    2. Also, Could you make changes at the OVP/OTP pin as shown below.

    3. Connect 4.7uF capacitor at the V5P

    4. Connect a 100uF at the VCCP.

    Let me know your observations

    Regards

    Manikanta P

  • Hello Manikanta,
    Sure, I'll apply all mentioned above to my circuit.
    Waiting for __02 chips samples.

  • Hello Manikanta,
    I have some updates.
    I still facing difficulties, but at least I know what is causing failure.
    First of all:
    - I changed component's values, as you suggested (all circuits fed by V5P LDO)
    - I removed HV series resistor, to disconnect HV current source and reduce amount of failure reasons.
    - I disconnected charge pump, designed to supply chip during normal operation (C24 capacitor).
    - I supplemented Vcc pin with extra 47uF ELCAP, connected in very close proximity to the MLCCs, soldered in a very close proximity to the Vcc and GND pins, respectively.
    -I supplied Vcc with 16V from precise laboratory power supply.
    -Finally I have got _02 chip version with integrated HV current source (but PIN1 I left isolated, to do not use HV current source)

    So, I started testing, but could get V5P voltage, whatever I tried to do.
    After re-soldering chip, I found V5P voltage available and chip's attempts to start-up.
    Throughout probing, turning ON and OFF external 16V, I suddenly found absence of V5P
    Omitting couple of hours of exercises, aiming understanding the nature of V5P LDO failure, I found the scenario:
    1 or more voltage interruptions at the Vcc pin, created by manually operated ordinary switch, leads to V5P LDo failure.

    What is interesting, LDo doesn't fail completely.

    Look at the pic below:

    First spur appears when I apply 16VDC to Vcc pin.
    Seems LDO tries to develop 5V but fails due to some reason.
    Second spur happens at the moment Vcc pin voltage drop in a moment I disconnect it from the external power supply.

    I hope this information will be helpful for you and development team.
    Moreover, hope you can suggest me the way to deal with this issue.

    Do not close thread please, I'll keep it updated as only will get new data.



  • Please give us few days to respond.

    Thanks

  • Hello Ning,
    Sure, take your time.

    I'll just supplement discussion with one more update.
    Yesterday I finished with situation, when integrated LDO fails during the Vcc voltage ON-OFF-ON.
    Today I soldered new chip, but V5P doesn't establish, as it did day before, in case of fresh chip soldered.
    I checked the overall load, connected to V5P, it's overall resistance is ~430kOhm (chip is removed).
    I'll leave captured V5P and Vcc signals.
    Vcc (16V) is supplied by precise laboratory PSU.
    V5P seems tries to establish, reaches level ~4.8V, but after short time LDO is turned off, V5P voltage falls down in a natural way due to the V5P cap discharge through the TSET and LL circuits.



    BLUE - Vcc voltage (HV current source series resistor populated, 380VDC applied)
    YELLOW - V5P voltage.

    Thanks.


    P.S. I have noticed one more suspicious behaviour.
    At the OTP pin no voltage at all.
    Complete silence.

    I compared with EVALPCB, there is a voltage drop on resistors, as expected.

  • Hi Alex,

    This could happen when TSET voltage is out of range. Could you let me know what values you are using at TSET.

    Also, could you share the captures of TSET and V5p together.

    Regards

    Manikanta P

  • Hi Manikanta,
    Sure, here you are :)



    YEL- V5P
    BLU - TSET

    So TSET voltage is ~500mV during the yellow signal highest level

    First yellow spur at the moment I apply 16V to the chip.
    Second one at the moment I disconnect 16V from the chip.

    HV current source isn't used (series resistor DNP).

    regards.

  • Hi Alex,

    Could you try different sets of TSET values: Use the design calculator to find out the values.

    Let me know if you still sees the issue?

    Regards

    Manikanta P

  • Hi Manikanta,
    V5P voltage issue solved.
    The reason for failure was a too large filtering cap connected to the TSET pin.
    I placed 100nF instead of 220pF, shown in EVB. The RC constant was to large, and IC didn't pass initialization.

    Going to apply HV and start switching.

  • Hello Manikanta.
    I have a question regarding the LL pin.
    I would like to completely OFF burst mode for debug purposes (for now converter starts, but seems switches to burst mode, and I can't control it).
    For now, LL divider values as per EVB schematic, but I want to deactivate burst mode completely.
    I checked the data sheet, there is an information about particular (VLLA-VLLB) voltage, deactivating burst mode.
    I can't recall it 100%, but I believe, I have seen here in other thread, recommendation to tie LL pin to GND, to completely OFF burst mode.
    Could you please tell me, whether chip detects LL connection to GND (VLLA-VLLB below 0.176V) and switches BURST mode OFF, or not?

  • Hi Alex,

    connect LL pin to Ground of the IC. That would deactivate burst mode completely.

    Regards

    manikanta P

  • Hello Manikanta,
    thank you for support.
    I shorted LL pin to GND, to avoid BURST mode.
    I applied as usually 16V to Vcc, and 380DC to HB stage.
    For less than a second, converter started.
    I caught by my eyes, voltage at the E-load increased to desired 48V and higher, to ~57V...
    Then all gone.
    I have found Rboot resistor burned.
    I changed it back to 2.2Ohm. (4.7Ohm||4.7Ohm, 0603).
    Now I see converter tries to start-up, both LO and HO drive Fets, at the HB middle point I do see start-up sequence of pulses, but after ~60 pulses, switching is terminated:

    HB swithing

    I checked CS pin, and found strange picture:


    a) Current rises in not a linear way.
    b) I have constant level of 1V at the CS pin, as long as 5V is generated by V5P.
    c) the peak value is ~6.5V, what is higher than highest CS threshold (there is no mistake with probe scaling factor).

    If you can commend situation by somehow, I'll appreciate.

    P.S. The Uout voltage starts to rise, during the start-up procedure.
    reaches ~16V of 48V desired.
    Hence there are no short circuit at the output,



    P.P.S
    I have found CS signal, captured before disabling BURST mode.

    The current during start-up showing fully shorted transformer, the only resonant inductance acting as a reactive element.


  • Hi Alex,

    Could you apply some load at the output (ex: 1A) when disabling the burst. Otherwise during no load, the switching frequency will be very high that leads to rise in output voltage due to the parasitic capacitances. During startup, Magnetizing inductance will be shorted by the output cap which is at 0V. So, you can expect the ISNS to be triangular during startup.

    Could you reduce the ISNS resistor value since its exceeding OCP threshold. Also, Could you use the right value of zener diode at the OVP/OTP pin to protect against the output over voltage.  Could you confirm which fault is being triggered (is it due to OCP?)

    Cold you share the feedback circuit schematic?

    Regards

    Manikanta P

  • Hello Manikanta,
    Thank you for the support advises and hints.
    Seems I destroyed something due to over-voltage, upon shorting LL to ground.
    I checked rectifying diodes (SYNC RECT. IC is deactivated, no Vcc applied, so only body diodes rectifying), output caps, etc, all seems to be good.
    - I'll follow your recommendations, will preload output again and reduce CS resistor.

    >>Could you use the right value of zener diode at the OVP/OTP pin to protect against the output over voltage.
    - OVP zener isn't present at PCB at all. Will be used in next revision.

    >>Could you confirm which fault is being triggered (is it due to OCP?)
    - I can't understand what fault resets the chip, whether it is OCP protection, or detection of capacitive region.


  • Mostly I believe its due to OCP since ISNS reaching more than the OCP threshold.

    Please follow my suggestions in my previous thread.

    Regards

    Manikanta P