Tool/software:
We currently use the slope compensation feature of this chip as shown in the D.S. Fig 11a - in 11a, slope compensation is only applied to PWM operation and does not affect current limit. I used the formula in the D.S. to calculate the slope compensation resistor and right now it is 3k3 ohms.
I am finding in our application that I get a lower current limit trip point at higher input voltage; i.e., a lower input voltage gives us higher current output capability. With an input range of 40V to 56V; the output current limit trip point varies from about 18A at 56V input to 20A at 40V input. Our output voltage is constant at 45V. We do use a transformer for isolation.
I increased the capacitor value in the RC filter ('Rfilter / Cfilter' shown in D.S. Fig 11) which helped to reduce the difference in current limit somewhat, but I want to improve it further.
Should I incorporate slope compensation into current limit? If so, I don't see how the example in the D.S. can work; in Fig 11b it shows the RAMP and CS pins are shorted together for this purpose. But if there is no resistor between the two pins, how will there be a slope compensation signal for the PWM? Can you provide some method or formula or show I can implement this?
Or should I just experiment with the RC filter further?
Hi,
The issue is due to the current reaches a same threshold faster at higher input voltage, so not the slope compensation issue but the current sensing issue. You need to lower current sensing resistor value to achieve higher input voltage current to meet your specs. Then increase your component current rating to tolerate lower input voltage higher current which would affect the OCP threshold so if you need precise OCP, you need to add OCP on the secondary side.
I know the slope changes with input voltage. Can you comment about increasing the RC filter capacitor? It does improve this.
What is the purpose of adding slope compensation to the CS pin as shown in the data sheet Fig 11b? What does that achieve?
Hi,
RC filter would slow down the peak so a previous current peak without RC cannot reach the same peak after adding RC or increase RC at higher input voltage so allowing higher peak current before trigger current limit then your output current gets higher.
It looks Fig 11b can help balance current between low line and high line input voltages, since low line compensation time will be longer than high line so current limit is adjusted at different input voltage. At low line, current limit becomes lower and high line becomes higher. It looks you can try this to see if this can improve the current limit different from your current Fig 11a setup.