LM5122: Damage occurs when started up with pre-biased load

Hi Bailey,

Thanks for using the e2e forum.
I am sorry to hear there are problems with your LM5122 design.

Just to narrow down the root cause, can you confirm the following:
- "The IC is fried" means only the IC is taking damage, all FETs and external components are still fine?
- What type of damage can be seen? Does the IC do not start operation anymore, or are there internal shorts, e.g. from SW to GND, or from VIN to GND?

If only the IC is damaged, there might be an overvoltage event at one of the pins that exceeded the abs max values.
For example, if there is an overshoot on the SW pin after starting to switch, it could burn the IC.

Do you also have the powerstage schematic available? (inductor, input/output caps and MOSFETs?

Thanks and best regards,
Niklas

Hi Niklas, thanks for your response. As far as I can tell, only the IC is taking damage. External components have been checked and the circuit is operational (with resistive load) by simply replacing the IC, no need to replace FETs. 

The IC has internal shorts from SW-GND. Can you think of what behavior from the circuit would cause an overvoltage event at one of the pins with a pre-biased load, but operate normally with a resistive load? Or perhaps, the IC is sinking current for some reason to try to regulate voltage during soft-start? I can't think of exactly why this issue occurs when the output is a battery pack but not the resistive load.

I've attached the power stage schematic. Thanks. 

Hi Bailey,

Thanks for the additional explanation.
I am also confused that the design only works with a resistive load.
A short form SW to GND would most likely be the result of going above the abs max voltage of the pin (105V).
As the target voltage is only 70V, this would imply that either there are very strong overshoots, or the design is running unstable.

This can be measured if you connect a probe to the Vsw testpoint 5011.

To rule out a stability issue, I would suggest to optimize the compensation network (R16, C17, C18).
According to our calculation tool, the system has a rather low phase margin in the current state. We recommend >60 degree for a stable system.
You can find the calculation tool here:
https://www.ti.com/tool/download/LM5122-BOOST-CALC

Best regards,
Niklas

Can you provide any additional information on how the compensator should behave during startup into a pre-biased load such as a battery. In this situation, it seems to me that the soft-start functionality may actually be working against you, trying to regulate the load to a lower point.

Hi Bailey,

The softstart ramp up the output reference voltage, meaning the device is meant to slowly ramp up the output voltage from 50V to 70V with a linear slope.
The load is relevant in regard to the overcurrent protection. During ramp up, the overall load is higher, as the output capacitors are charged as well.
OCP is still active during the softstart, so if the device cannot support both the load and the charging of the output caps, it will trigger OCP, limit the duty cycle and enter hiccup mode or never reach the target output voltage.

Normally this should not damage the device or lead to higher voltages on the SW pin.
This is the reason why I am asking for the Vsw testpoint signal, as I hope to get more information on how the device behaves during the startup time.

Best regards,
Niklas

Hi Niklas, 

Thanks for your response. The converter has RES grounded, so hiccup mode should be turned off. I expect the batteries to be current limited initially and then be brought up to target voltage as they are charged. Also in reference to your previous message, that schematic is slightly out of date and the compensator components have been updated for a higher phase margin. The compensator is operating stably with resistive loads. 

I do have some more results to share with you. When I run the converter to a pre-biased load but with a diode on the output in front of the batteries (thus blocking any backwards current from the load that's occurring), there are no issues. Based on my scope captures, it seems that it is just doing a successful soft-start charging the output caps until they exceed the battery voltage + the forward drop of the diode, turning it on and beginning charging. 

My theory is that without the blocking diode, during soft-start the controller is trying to pull the output voltage (initially the battery's OCV) down below the target voltage (because of soft-start). To do so, it would turn on Q2, resulting in a negative voltage across the inductor. Perhaps the DEM response is not fast enough to turn-off the negative current before the IC has sunk some current that results in the damage seen. I do have a filter on CSP-CSN with 100 Ohm resistors and a 10pF capacitor across those two terminals. I am wondering if that filter may be slowing down the current-limiting and DEM responses from the IC which are meant to prevent damage.

Let me know what you think or if you have any questions or other ideas for possible solutions.

Thanks

Hi Bailey,

Thanks for the update.

I understand your theory, but there are some points about the device which do not add up.
To only turn on the high side FET, the device would need to be operating in bypass mode.
This mode would be activated, if VIN is higher than the target output voltage, BUT this mode is inactive during softstart. The device always starts up in DEM, independent of the MODE pin connection.
While the softstart reference ramps up, the device should do nothing until the reference goes above the actual VOUT voltage.
E.g. if Vin is 50V and Vout is precharged to 65V, the device should start operating once the reference ramp target reaches 65V and then only starts boosting from there to the final 70V target and complete softstart there.

The filter on the current sensing should not affect the switching delays either.

If it is actually the case that the high side FET opens and allows negative current, it might be possible that the current flows all the way to the input and puts the CSN pin above abs max, as it has lower ratings than the SW pin, and causes internal damage through the ESD structures.
However, it is difficult to confirm such theories without looking at waveform measurements.

Best regards,
Niklas

Here you can see the high side gate signal (Q2G, Ch1, yellow) during startup with Vin and Vout (Ch3, purple). You can see an extended pulse during startup when Vin exceeds UVLO, part of what led to my theory about reverse current shoot-through. However, it's hard to say if this behavior exactly matches what is happening when the output is directly connected to the battery because there is a diode between the output caps and the battery load to protect the circuit. Without that, the IC would sustain damage and need replaced. I will plan to set up a remote sense where the feedback loop is tied to the battery load even with the diode protecting the circuit to try to deduce actual behavior. Let me know if you have any further thoughts about this or ideas. Thanks.

Hi Bailey,

Thanks for attaching the waveform of a "good" startup with resistive load.

Here are some general comments I have:
- With a charged battery connected to Vout, there is negative leakage current at the high side FET even before turn-on, but this leakage should be small enough that it will just discharge via the UVLO voltage divider and not charge up VIN
- If this larger HO pulse also appears during startup with the charged battery connected, there can indeed be a stronger negative current flowing from Vout to Vin. However, the device should realize that Vout is above target during softstart and should stop switching, thus disabling both LO and HO
- The inductor will still shift current to the input side after the HO pulse and the SW voltage level could go negative

- In that case, the body diode of the LO side FET should become conducting, so this would only be a problem if the body diode acts to slow and the device is already damaged from the negative current.

If this is the root cause for the damage, it would be solved by placing a diode from GND to SW (in parallel to the LO side FET), to avoid negative voltage levels on the SW.

Best regards,
Niklas

Hi Niklas, 

Thanks for the comments, I will take them into consideration. 

Meanwhile, do you have a clear explanation of why I'm seeing that extended high pulse on HO during startup? I thought that this would only occur in bypass mode which shouldn't be in effect during soft-start? Based on the schematic or just intuition, do you know why this might happen? 

Thanks,
Bailey

Hi Bailey,

I will involve our design engineer to get more insights on the internal behavior which creates this HO pulse you are seeing  on bench.

Please allow me some time to get feedback.
I will get back to you by tomorrow.

Best regards,
Niklas

Hi Bailey,

It seems like there is an argument against the negative current inrush at turn-on.
When the device starts operating, it switches with the LO side first and only then add the HO side switching after some pulses.
This is to avoid starting with negative current bias in the inductor.

I tested this in the lab to confirm this on our EVM:

Looking back at your schematic, I noticed the SS caps is 1nF, which leads to a very short softstart time.

Would it be possible to increase the SS capacitance and repeat the same measurement?
In addition, could you probe the LO driver signal as well to confirm that the low side starts switching first?

Thanks and best regards,
Niklas

Hi Niklas, thanks for gathering more information. You can see in the attached screenshot that the extended Q2G pulse seen in the previous screenshots comes before LO starts switching and is equivalent to ~50 switching periods. In addition, the pulse is at around 10V (QG2-SW), this is higher than the normal switching level, implying that BST-SW > Vcc which I wouldn't expect. In addition, I built an identical, asynchronous version of this circuit with a diode in place of Q2 (severing the connection to SW pin, tying BST to Vcc and grounding the SW pin, as seen in the SEPIC example in the datasheet) and everything is working as expected without issue. This leads me to believe perhaps there is something about my bootstrap circuit that is causing issues, let me know if you see an issue there. The bootstrap diode is SS2PH10-M3 and is in series with a 5 Ohm resistor to reduce current spikes. This can all be seen in the previous schematic.

In the meantime, I can increase SS and see how this affects behavior. Thanks for your continued support.

Hi Bailey,

Thanks for the additional measurements.

This all contributes to the theory of negative current in the inductor.
If the SW node goes negative, it also explains why BST-SW > VCC.
BST gets charged with the SW amplitude, which is VOUT (70V) to GND (0V). If SW goes negative, the charge level is VOUT (70V) to GND-overshoot (-5V).
So the HO signal is 5V larger after a negative overshoot on SW.

The abs max ratings say the SW can support -5V spikes, but larger spike can damage the device, which I assume happens when starting with pre-charged load.

I made some more tests on our EVM board.
I tested with the default 100nF SS cap and a 1nF cap as in your application.
I was not able to re-create the long HO pulse.
However, the larger SS cap showed a more stable start-up.
Please see attached slides.
LM5122-startup.pptx

If the long HO pulse is still visible with a larger SS cap, it might be necessary to implement a fast diode from GND to SW. This will reduce the negative spike at the SW pin and prevent damage of the device.

Best regards,
Niklas

Hi Niklas, 

Thanks again for the responses. I have a few more captures to share with you of the synchronous boost with a resistive load. The first capture shows SS pin (Ch1) and Q2G (Ch3). As you can see the long pulse is occurring before SS has reached 1.2V, confirming that bypass mode shouldn't be active during this time (as per your previous post). The second capture shows the SW node and Q2G, demonstrating that Vsw is not spiking negative during the long HO pulse (or directly before). The third capture show the rise of BST-Vsw (Ch3), which if you backcalculate knowing that Cbst=0.1uF, matches almost exactly the 200uA from the charge pump, meaning the excess voltage across Cbst likely comes from the charge pump not from a negative SW spike. 

Can I ask what jumper configuration you had on the EVM during tests (dictating device operating MODE). In the synchronous boost converter, the MODE pin is tied to GND, meaning it should see conventional pulse skipping in DEM mode. 

Thanks again for your help. 

Hi Bailey,

Thanks for your measurements and the update.
I understand that the higher pulse being caused by the charge pump is more likely in this case.
Still, I need some additional time to look into the root cause of the abnormally long high side pulse.

I have been testing in FPWM mode so far.
I will change the MODE settings to see if I can see a difference. I will also check once more with our design team for further explanations on this.

Please expect a reply before Friday.

Thanks and best regards,
Niklas

Hi Bailey,

Thanks for your patience.
Through some further bench tests, I was able to recreate your measurement results to some degree.
The MODE change did not affect the startup behavior, but I saw a long on-pulse in a startup with FPWM mode.

This pulse is merely 40us long, but it is still much larger than the fsw.
As this can be re-created on any device, I would not assume it is a device failure.

I am still in discussion with our designer to get a clear explanation for this behavior.

To continue investigation on bench to find the root cause for the device damage, I would need to set up a destructive test with a charged battery on the output side. If we could see how the SW, HO and LO signals behave and if there are strong over/undershoots right before the device damage occur, we could propose a solution on how to avoid damage.

I will keep you updated on tests results by middle of next week.

Best regards,
Niklas

Hi Niklas, 

This is very interesting to me. Thanks for sharing, I appreciate the hard work you've put into this support. Looking forward to hearing if you discover a solution. 

Thanks,

Bailey

Hi Bailey,

Sorry for the long delay on my response.
I have run some tests with a pre-charged 47mF cap at VOUT to imitate your setup with connecting a charged battery.
I was not able to recreate any longer HO pulses than seen in my previous message, nor did I see any damage on the IC.

As I cannot re-create the behavior on your side, it is difficult to track down the root cause for your initially damaged IC.
I am not sure if I already asked this, but how many ICs good damaged this way so far?
There might be no way around purposely destroying another IC this way to prove it can be recreated consistently, and to measure the SW / HO / LO voltages during the failure event.

Best regards,
Niklas