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TPS92692-Q1: Reasons for longer Turn-on and Turn-off first period when using PWM dimming

Part Number: TPS92692-Q1

Tool/software:

Hi Team,

Customers are evaluating the TPS92692-Q1 on its EVM, and for the tested waveform showed in datasheet, customers have below questions:

As the below figure showed in datasheet, when using external PWM dimming, the first NMOS turn on time after the rising edge of VPWM is longer than the static ones.

Customers would like to know why the first Ton time is longer and why the current through the Ris is also higher? And how can they calculate the first Ton time and peak current that might flow through the NMOS in first period? Customers might need the method to confirm the time in their design. 

BR,

Manu

  • Hi Manu,

    This is the response due to your compensation network. Initially there will be a large spike due to the device turning on and then the control loop will compensate accordingly. This is very typical with all devices that utilize a control loop. The response time can be tweaked by varying the values of your compensation network, however, it looks like your customer did a good job.

    Out of curiosity, why is this marginal difference in time important to the end customer, what are they trying to achieve by predicting this minimal delay?

    Best,

    Daniel

  • Hi Daniel,

    Thanks for your reply, as I mentioned in E-mail and another thread, customers are trying to implement a 105W load, so they curious about the delay for the first period and the largest overshoot current that the inductor can reach in first period.

    From the explanation you made, it seemed that it can only achieved by the tests in real cases.

    BR,

    Manu

  • Hi Manu,

    Thank you for your reply. Please let me know if there is anything I can do to further assist you. To reiterate, there will almost always be some margin of time  the converter needs to regulate itself.

    Best,
    Daniel