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Original question:

TPS25947: looking for a power mux solution

TPS25947: TPS259470 Priority Power Mux Problem

Caner Alp
Prodigy 115 points
Part Number: TPS25947

Tool/software:

Hi, 

I am trying to make a priority power mux. I have seen the suggestions on the forum TPS25947: looking for a power mux solution - Power management forum - Power management - TI E2E support forums .

However, my implementation doesn't work. When I supply +VIN1 and +VIN2, it works. However, +VIN3 and +VIN4 don't work. I measured the U6A pin 1 and 2, I get 0V, hence 0V on the OVLO pin of U7. 

In this case I assume that U7 doesn't supply +3V3, therefore the pull-ups don't work. Do you have any other suggestions? 




Regards,
Caner

  • 0
    TI__Mastermind 38135 points

    Hi Caner,

    Caner Alp said:
    I get 0V, hence 0V on the OVLO pin of U7. 

    This looks correct. For this condition, I would expect the device to turn on. 

    Caner Alp said:
    In this case I assume that U7 doesn't supply +3V3, therefore the pull-ups don't work. Do you have any other suggestions? 

    I didn't fully understand this. By pullups do you mean the VIN3 is not coming at OUT pin?

    Since the OVLO signal is correct and U7 is still off, that means the issue is not in muxing implementation but rather near the device itself. Can you please measure the voltage of following pins of U7

    EN, AUXOFF, FLT, VOUT, DVDT

    Best Regards,
    Arush

  • 0 in reply to Arush Gupta
    Prodigy 115 points

    Hi Arush, 

    When I supply +VIN3 with 3V3, 

    • I measure 1.15V at the output VOUT 3V3. 
    • EN pin 1.7V
    • AUXOFF pin 1.15V
    • FLT pin 1.15V
    • DVDT pin 1.15V
    • OVLO pin 1.15V

    I also measure the inputs and output of U6A, I get 0.7V for the both inputs and 1.15V for the output which goes to OVLO pin. And according to the specs, the threshold for OVLO is 1.183V. I think this is the problem.

    It is strange that the OR gate produces high output even with insufficient voltage supply and 0.7V inputs. But at first the fuse should get enabled, should I have a delay on OVLO pin maybe to solve this? 


    BR,
    Caner

  • 0 in reply to Caner Alp
    TI__Mastermind 38135 points

    Hi Caner,

    I think you are using OR gate in threshold grey zone i.e. between maximum logic 0 and minimum logic 1 voltage and this is causing incorrect behavior.

    Best Regards,
    Arush 

  • 0 in reply to Arush Gupta
    Prodigy 115 points

    How can I use the OR gate in the grey zone? The eFuse is supposed to be enabled for 3V3, then the defined logics should come. However what I realized is that before even eFuse turns off, OR gate disables the device. So I pun a delay, it seems solved for now.