TPS92520-Q1: The V5A&V5D noise and ripple requirement of TPS92520 and relationship with Cbst or bootstrap capacitor

hongwei geng

Prodigy 60 points

Part Number: TPS92520-Q1

Tool/software:

Hello ,TI team

i want to know the V5A&V5D noise and ripple requirement of TPS92520,the datasheet does not show this content,

or the TPS92520 V5A&V5D do not care the ripple and noise,right?

6 months ago

0 fhoude 6 months ago

TI__Mastermind 23246 points

We do have recommended min V5D input capacitance that is a function of the bootstrap capacitor used, where we state a 10x rule which is designed to ensure when the bootstrap capacitor (Cbst) is charged up the V5D supply doesn't droop down low enough to trigger UVLO of V5D/A. For example if Cbst is 0.47 uF, then V5D input capacitance should be 4.7uF. We also recommend a 0.1 or 0.01uF capacitor in parallel at the pins for minimizing ripple and noise.

https://e2e.ti.com/support/power-management-group/power-management---internal/f/power-management---internal-forum/1241964/tps92520-q1-sch-review/4698752?tisearch=e2e-sitesearch&keymatch=TPS92520%252010x#4698752

0 hongwei geng 6 months ago in reply to fhoude

Prodigy 60 points

So,if design follows up the datasheet guideline,the ripple or the noise of V5D&V5A can reach up to 5% of V5D&V5A?

0 fhoude 6 months ago in reply to hongwei geng

TI__Mastermind 23246 points

Where did you get 5% ripple from??? for the most part the ripple is small and it is a don't care if you follow the recommendations in the applications circuit.

0 hongwei geng 6 months ago in reply to fhoude

Prodigy 60 points

OK,i need the ripple criterion of V5D&V5A,as we know,different supplier capacitors have different DC bias value ,if we change the supplier from A to B,we don't take the capacitor DC BIAS into account in TPS92520 circuit?

+1 fhoude 6 months ago in reply to hongwei geng

TI__Mastermind 23246 points

5% ripple is acceptable for peak to peak ripple but you must adhere to the 10x of Cbst (boost strap capacitor) guidelines for V5D/A capacitance. Cbst gets charged by V5D/A capacitance and we need to avoid having the voltage on V5D/A from hitting UVLO (4 V) with some margin during the charging of the boost strap capacitor (Cbst) by the LS FET. It is a simple charge balance equation. Below you see if you use 10x rule then V5D never gets below4.55V. Given the larger capacitance needed for this requirement the rippl should be very small, less than 5%.

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TPS92520-Q1: The V5A&V5D noise and ripple requirement of TPS92520 and relationship with Cbst or bootstrap capacitor