BQ76952EVM: External FET's Balancing Issue – All Cells Including Lowest Being Discharged

Hi Vamsi,

For 4s configuration, you should connect cells as the recommendation in:

• How should I connect cells to the BQ769x2 family of battery monitors?

VC9-VC10 need be connected to actual cells. And you need to configure Settings:Configuration:Vcell Mode properly.

The log is hard to read. Are you using the autonomous balancing or host-controlled balancing?

BRs

Kian

HI Kian Lin

Is it mandatory to connect to vc9 and vc10 because right now balancing is starting without any errors. With current configuration it did balancing with internal FETs, but with the same configuration it is having voltage fluctuations when doing with external FETs. I think that is the reason for continuously draining of the battery. 
Regarding the Log, i downloaded it from BQStudio and sent directly. can you tell me what all values do u want to look, i will filter them and send.


Thank you very much for the help

Hi Vamsi,

Can you open top-of-cell balancing without VC9-VC10 connection?

Vamsi Tungala said:

With current configuration it did balancing with internal FETs, but with the same configuration it is having voltage fluctuations when doing with external FETs. I think that is the reason for continuously draining of the battery. 

I meant you control the balancing by AFE itself or by the MCU command?

Can you share the.gg file and the log of battery status, CellBalancingActiveCells and CellBalancingPresentTime?

BRs

Kian

Hi Kian Lin 

Kian Lin said:

I meant you control the balancing by AFE itself or by the MCU command?

I am using AFE, not MCU Command .

Kian Lin said:

Can you share the.gg file and the log of battery status, CellBalancingActiveCells and CellBalancingPresentTime?

Attached the log file and .gg file as requested.4s_balancingExternalMaxi.gg.csv

9.log

Kian Lin said:

Can you open top-of-cell balancing without VC9-VC10 connection?

I didn't understand this question. What do you mean by top of cell balancing?

Thank you 

Hi Vamsi,

Sorry for the misleading. I thought you are using BQ76942... I mixed your question with another thread.

I revisit this issue. The question is why external balancing FET still on even with internal FET turn-off, right?

Did you test the waveform of below points circled in green?

You can also read the Cell Balancing Active Cells() to see if AFE activate the balancing on unwanted channels.

BRs

Kian

No, actual problem is cell balancing is working fine with internal FETS, voltage reading or stable and stops the balancing when it is under threshold vales. But when  i am using external FETs, voltage readings are fluctuating going up and down, because of this balancer is always turned on and draining the battery continuesly. Even the lowest cell is being balanced and its voltage is going down even more. 

How can we stablize the voltage reading for external FETS?

I hope you get the problem. Otherwise let me know. May be we can connect over mail or anyother platform and clarify things easily.

Hi Vamsi,

Are you connecting the external FETs like the image I show you? Can you take a screenshot of your schematic?

BRs

Kian

This is the schematic from our custom PCB we made, which was not working due to some design issues. But i am connecting EVM board to this part of the schematic using some wires for external FETs. 

(Please ignore FETs direction in this schematics. Actual pcb has correct orientation.)

Hi Vamsi,

The sch looks good.

Can you test a waveform of the points i showed before?

Are you using resistor ladder to simulate cell? You need to use actual cell for the balancing test.

BRs

Kian

Kian Lin said:

Can you test a waveform of the points i showed before?

Sorry, I didn’t understand the points you meant . Can you be more specific, it would be better if you can point out in the schematic where i should check the waveform.

Kian Lin said:

Are you using resistor ladder to simulate cell? You need to use actual cell for the balancing test.

I using real cells with 4s configuration, connected to VC0 VC1 VC2 VC15 VC16. 

Hi Vamsi,

Vamsi Tungala said:

But when  i am using external FETs, voltage readings are fluctuating going up and down, because of this balancer is always turned on and draining the battery continuesly

You said you have fluctuant voltage reading when using external FETs. Taking cell 2 as example, I want the waveforms across R56, R53, Cell2-to-Cell1 and VC2-to-VC1. 

Vamsi Tungala said:

Even the lowest cell is being balanced and its voltage is going down even more. 

Also, can you clarify more for this issue?

Vamsi Tungala said:

I using real cells with 4s configuration, connected to VC0 VC1 VC2 VC15 VC16. 

This configuration is workable but the four cells with have different balancing 'duty cycle' if using auto-controlled balancing.

It will be better if you can show some data or scopes to help me better understand your issues.

BRs

Kian 

Hi Kian

I have attached the scope images as requested and Excel sheet with log data and graphs collected during the testing. log1 file is for across resistors and log2 is for across cells.

Kian Lin said:

Even the lowest cell is being balanced and its voltage is going down even more.

initial cell voltages are as follows from log2 file

from these vales cell 1 is lowest of all and rest of the cells should balance and cell 1 balancing circuit should not be activated but you can observe cell 1 is being activated (sample number 28 to 35 from log2 file). In the graphs, you can see the voltage fluctuations and all cells being balanced. As per my understanding lowest cell should not be balanced, correct me if i am wrong. 

Scope screenshot: 
Across R24 Cell 1 active

Across R24 Cell 2 active

Across R21 Cell 1 active

Across R21 Cell 2 active

vc2-vc1 cell 1 active

vc2-vc1 cell 2 active

c2-c1 cell 1 active

c2-c1 cell 2 active

8228.log1.xlsxlog2.xlsx

Schematic

Please let me know if you need more data. 
i also screen recorded during testing for reference you can find them in this link

Thank you
Vamsi Tungala

Hi Kian Lin

Apart from the above data i also have saved graphs for both internal and external fets from BQ Studio

Internal FET graphs, you can see the graphs and they dont have fluctuations much except for the cells which are balancing C1 and C16. after some time balancing is done and it stopped the balancing.

External FETs: this graphs is for external FETS and we can clearly see the voltage fluctuations for all cells. Balancing never stopped and it continued to drain the batteries.

Thank you
Vamsi Tungala 

Hi Vamsi,

I believe you have good SW and HW configurations. Only one thing need to check with you:

• Did you connect the external circuit to BQ76952EVM connector with the R14-R28 connected? The EVM board also has this circuit on board. You should remove it.

The scope you attached does show the lowest cell was balanced. And the logged voltage is in chaos which cannot show me more clues on it. Something strange to me is why your cell1 voltage had ~20mV error when no cell was being balanced?

Did you use the real cell for testing?

I will be out for next two weeks. Other colleagues will response you for this questions.

BRs

Kian

Hi Kian Lin

Kian Lin said:

Did you use the real cell for testing?

Yes i am using real cells for testing. 

Kian Lin said:

Did you connect the external circuit to BQ76952EVM connector with the R14-R28 connected?

Did you mean R2-R24? yes, they are still there. 

I will remove these and check. Should i also have to remove capacitors?

Thank you 
Vamsi Tungala

Hi 

Please find the test graphs and logs collected after removing the resistors. I don't see any difference. Issue is still there. 

log3_no_resistors.csv

Hi Varnsi,

I'm not well versed on this case, am trying to help some while Kian is out.  As I scan through this, I just want to make sure you have the Vcell Mode setting correct for the cells you are using.  I noticed in a gg file you have Vcell Mode = 0x8007, which indicates you are using VC16-VC15, VC3-VC2, VC2-VC1, and VC1-VC0.  Then do you have VC4...VC15 pins all shorted together?  If the Vcell Mode isn't set properly, the device may be trying to balance a cell while a measurement on that cell is underway, causing corrupted measurements.

It seems Cell-1 is bouncing the most here in your log.  You might put a scope on cell-1 while balancing is underway, just to make sure there isn't some transients getting onto the cell voltage.  Your scope plots above are very zoomed out, can you zoom in to see maybe 50mV/div, to see if changes on the cell voltage may be similar to what is seen in the log (which is ~100mV in some cases)?

Thanks,

Terry

Hi Terry 

Thank you for your response

-Terry said:

I noticed in a gg file you have Vcell Mode = 0x8007, which indicates you are using VC16-VC15, VC3-VC2, VC2-VC1, and VC1-VC0.  Then do you have VC4...VC15 pins all shorted together?  If the Vcell Mode isn't set properly, the device may be trying to balance a cell while a measurement on that cell is underway, causing corrupted measurements.

you can refer to the image i uploaded for connections in the previous messages. Let me know if they are any issue with that.

Kian Lin said:

• 

-Terry said:

It seems Cell-1 is bouncing the most here in your log.  You might put a scope on cell-1 while balancing is underway, just to make sure there isn't some transients getting onto the cell voltage.  Your scope plots above are very zoomed out, can you zoom in to see maybe 50mV/div, to see if changes on the cell voltage may be similar to what is seen in the log (which is ~100mV in some cases)?

Please find scope images of as you asked with 50mv at cell1 i took multiple screen shots. These are during cell 1 balancing.


Please let me know if you need anything else.
If possible it would be better to arrange a call to clarify things faster. its been so long that we are trying to test this IC and we need to find solution ASAP.

Thank you 
Vamsi Tungala

Hi Vamsi,

I am back to office now. Feel free send the meeting invitation via email.

I am in GMT+8 Asia time zone and prefer next day afternoon(mt time). 

BRs

Kian

Hi kian

Thank you for the response.

where can i find you email? 

i live in Germany, will it be okay to have meeting at 5pm (gmt +8 )for you? If not please let me know will plan accordingly.

Thank you 

Hi Vamsi,

The time is okay. My email is kian-lin@ti.com. You can find it in myTI information.

BRs

Kian