LMZ10501 Soft Start Rate

Hello Phil, 

The constraint is that FB has to be above 375mV at the end of the ~75us so that the output short circuit protection does not engage during startup. Higher Vcon capacitor can be used but that constraint must be satisfied. It may be possible to achieve 200us of soft start time but it depends on the output voltage setting, loading and output capacitor. I can try this fairly quickly and let you know tomorrow.

What I need is the output voltage setting, the input voltage, and the output capacitor they are considering. I will assume 1A load (worst case) unless you say otherwise.

Regards, 
Denislav 

I am attaching an excel calculator I put together to predict the softstart time. It is a bit simplified, but it is fairly close to reality. 

Regards, 

Denislav

3122.softstart_estimate.xlsx

Hi. Denislav!

I could not download (open) the excel file (attached one).

can you pls. forward me (bishnu.ban@tttech.com)!

regards

Bishnu

Hello Bishnu, 

Here is the file again. See if you can download it and if not, I will send it via email. 

7103.softstart_estimate.xlsx 

Regards, 
Denislav

Denislav,

One customer is also trying to get 200uS soft-start time on the LMZ10501 that is powering a FPGA:

    I have a question about the LMZ10501 switcher.  Id like to reduce the turn on ramp rate on one of my rails - my Spartan 6 FPGA has the odd requirement of a minimum power rail turn on time.  It currently comes up in about 100uS, and I'm shooting for more (>=200uS if possible). 

    The schematic I'm starting from looks very much like the 1.2V suggested circuit in Fig 10 of the datasheet.

The 1 nF cap and 534k/136k divider yielded a ramp time of approximately 200 us, but the 534k resistance exceeds the maximum recommended value on the LMZ's data sheet.  Keeping all parts within their recommended ranges, I don't think we could get the ramp time to exceed 100 us.

The data sheet mentions the Vcon resistor as adjustable for soft start, but then it also discusses the internal 75 us soft-start process used to scale up the switching frequency.  Indeed, we really didn't see any change in ramp time as the Vcon resistor changed from 470 pf to 1 nF (keeping the resistor divider as per the schematic).  We really have to slow the Vcon ramp way way down to get the output ramp to slow at all.  It seems that these parts are only designed for ~100 us ramp, and we'd have to violate their specs in some way to slow them down.

If it is okay to use the 534k resistor in the Vref to Vcon position, please let us know and we'll look at a BOM change.  Otherwise, please take this as feedback to engineering.  This digital rail switcher might not be as useful as we'd hoped if it's incompatible with Xilinx FPGAs.

Hi Ronnie, 

The suggestion for 80k to 300k Rt value in the DS assumes maximum output capacitance (per table 1). The 80k limit ensures that the Vref current is always under 30uA. The 300k limit ensures proper startup for all output voltages with max output cap.

The suggested range is conservative to cover all range and can be loosened for your particular condition. It is not a hard spec.

It is OK to use larger Rt resistor value or larger Cvc, as long as you don't stretch the softstart time too much. Too much, meaning that it results in FB voltage being lower than 0.375V after the 75us timer.  At that point feedback will be monitored for short circuit events and if it is not high enough,  the short circuit protection can trip during startup. The spreadsheet will predict this.

It looks like 534k and 1nF combination should work for your case.

Let me know if this makes sense. 

Regards, 
Denislav