TPS7H1101A-SP: TPS7H1101A-SP

Hi Kevin,

For this LDO, the key connections for parallel configuration are:

• Shared VIN and shared VOUT
• Tie SS pins together and tie EN pins together
• Connect FB pins to the same point of regulation, with a shared FB resistor network
• Connect the CS pin of one device to the PCL pin of the other, for both LDOs 

Each LDO should have its own 10nF COMP capacitor and its own input caps. I would also recommend splitting the SS caps and output caps so that they are placed locally near the pins of each device. 

Let me know if there is anything specifically I could clarify further, including with regards to component value selection questions you mentioned.

Thanks,

Sarah

Sarah,

Thank you for your response!

Datasheet does indicated the connections as described. 

RE:  "RCL"  (CS and PCL pin connections.)
Datasheet does indicates the "RCL" is optional... or suggests a value of 3.75K resistor for current > 6A.


For Example: 
My intended parallel use case does not demand increase the current output, but to lower power dissipation in the physical package.
Use cases:
1) VIN  =  5.0V - 5.2V; VOUT = 3.3V; Inom = 1.0A; Imax = 1.8A; Foldback = 2.0Amps
1) VIN  =  5.5V - 6.0V; VOUT = 5.0V; Inom = 1.0A; Imax = 3.0A; Foldback = 3.25Amps

Considering these conditions, a single part would dissipate in the range of 2.0 to 5.5 Watts (brickwall limiting). 
That is a bit too much heat for our comfort zone on a per part basis. 
Thus, we want to split that heat load between two packages for a lower thermal burden and increased reliability for each package.  

Can you confirm that for lower nominal currents, in parallel operation, these connections can/should be made directly?... with no interconnecting resistance?

Hey Kevin,

Thanks for expanding on your desired use case. My understanding is that the resistor between the PCL and CS pins is necessary regardless of whether or not the total load is larger than what a single LDO is rated for. 

This is largely due to the fact the there would be current sharing issues if one LDO went into foldback current limiting before the other could (due to mismatches between when the 2 parts enter current limiting). Using the RCL resistor to connect the CS pins to the PCL pins allows the CS pin voltage to drop below the 90% of VREF threshold as load increases, therefore disabling the foldback current limit mode. 

All the best,

Sarah

Sarah,

Thanks much for your reply.

The datasheet has pointed out an arbitrary value of 3.75k for the two "PCL" resistors required for sharing mode.

What is the best method for calculating the resistor value for proper sharing operation under all loads??

Does the TPS7H1101A Calculator worksheet (available from TI website) apply in these situations??