Quick review

Hi Craig,

Overall the main part of the schematic looks good, I do have a couple comments below:

Some amount of bulk input capacitance is recommended. The datasheet recommends at least a 10uF or 22uF ceramic capacitor in addition to the small bypass caps you have in the schematic. More bulk capacitance may also be required due to the relatively large 3.3uH inductor sitting directly upstream.

Due to the use of low-ESR ceramic output capacitors, a feed-forward capacitor may be required across R58. The need for a FF cap will depend on the stability performance, so adding a pad for one at least is recommended in this case.

The datasheet calls out an optional 1 to 10Ohm resistor in series with the BIAS connection to VOUT, as well as a 1uF or greater bypass capacitor from BIAS to GND close to the pin. While these additions are not required, if there is board space available they could be added for noise filtering to BIAS. 

What is the purpose of D16? I am unsure of it's function. I believe with the low current application, the DC power rating will not be violated, but adding bulk capacitance to PVIN may help with power spikes though this diode.

I did not review the pi filter on the output of the device (C16, L6, C17, and C18) as being placed outside of the feedback path should minimize it's impact on device functionality.

Thanks,

Andy

Hi Andy:

Thank you for the thoughtful review and I will dd the optional feed-forward capacitor and more bulk capacitance.  Honestly, I added the upstream inductor as an input filter and forgot that additional upstream bulk decoupling was now isolated by the added inductor so I will add more on the PVIN side as you point out.

I will also add the BIAS pin filter as you suggest.

As for D16, it is added because our input voltage could be as high as 34V, and that would violate the max PVIN of 32V.  As far as the power rating goes, our max load is 8V @ 0.3A = 2.4W.  Assuming 85% efficiency, the power drawn by the buck regulator should be less than 2.9W.  At our minimum input voltage of 18V, the input current will be 2.9/18=157 mA.  The Zener dissipation will be less than 0.62W.  I figured I had derated it enough.  Do you still see an issue?

Thanks,

Craig

Hi Craig,

Thank you for elaborating on D16. I have not seen this solution used before.

While I don't see any obvious issues with that method, typically we would implement a 32V Zener + resister to GND clamp to limit the voltage. Or a simple discrete LDO comprised of a resistor, Zener diode, and BJT to provide some pre-regulation (see SSZTC40 for more details on designing a discrete LDO).

The inductors used for the input and output filters are also much larger than I have typically seen, with additional bulk capacitance on the input, I don't think it should be an issue, but unless the upstream regulator is extremely noisy, a filter that large on PVIN may not be required. Are the downstream components extremely noise sensitive? Voltage ripple should not be extreme with this schematic, and switching noise can typically be blocked with a ferrite bead pi filter if required.

Thanks,

Andy