Tool/software:
Hi,
The user guide for TPS65941319-Q1 specifies pulling PMIC_nRSTOUT to VDA_MCU_1V8.
What would be the consequences of pulling it to VDD_MCUIO_3V3 instead?
Thank you.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Tool/software:
Hi,
The user guide for TPS65941319-Q1 specifies pulling PMIC_nRSTOUT to VDA_MCU_1V8.
What would be the consequences of pulling it to VDD_MCUIO_3V3 instead?
Thank you.
Hello Michael,
From a timing perspective if you look at the some of the sequences there are differences, on top of that you're trying to use a load switch to pull up to which is outside of the PMICs control. We can not enumerate all of the consequences as that is considered undefined, the above requirement is to satisfy ASIL requirements for integration.
You are welcome to do a failure analysis and we can assist you in a tailoring the FMEDA as a work product in your ASIL flow.
BR,
Nicholas McNamara
Hi Nicholas,
Sorry, I shouldn't have said VDD_MCUIO_3V3 specifically. Ultimately, what I'd like to do is use PMIC_nRSTOUT as an input to a AND gate. However, all the other signals on the AND gate are 3.3V and its minimum V_IH is 2V, so I was wondering if I could simply pull PMIC_nRSTOUT to a 3.3V rail. Instead of VDD_MCUIO_3V3, what about VCCA_3V3?
Thank you,
Michael
Hello Michael,
Thank you for the clarification!
While that would be permissible from a datasheet standpoint for the PMIC, be sure to double check the requirements on the PORz on the connected SoC.
I'm guess that you're using glue logic to block the PORz from toggling on the SoC side, just make sure the SoC pin is fine with bringing it up to 3V3, often times the lowering of the 3V3 -> 1V8 is due to the way the domains are powered and what they can tolerate under certain power configurations.
BR,
Nicholas McNamara