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TPS650864: Power on sequence setting and schematic review

Part Number: TPS650864
Other Parts Discussed in Thread: TPS650861, IPG-UI

Tool/software:

Hi team,

My customer is asking about the power-on sequence for TPS650864, which provides power rails for FPGA. The required timing sequence is as follows: BUCK1->BUCK2->BUCK6->BUCK3/BUCK5->LDOA2->SWB1_2->LDOA1->SWA1; How to configure? I have attached the TPS650864 schematics and the register settings, Please help to review that.. Thank you.

TPS6508641SCH.pdf

  • Hi Eric,

    Thank you for reaching out on E2E.

    TPS6508641 comes with default OTP settings.

    If the customer wants to use their own power up sequencing, they have to use use programmable TPS650861 device.

    Below is the link to product folder and datasheet.

    https://www.ti.com/product/TPS650861

    NVM programming guide can be found at,

    https://www.ti.com/lit/pdf/swcu188

    OTP generator file can be found at,

    TPS65086100 OTP Generator (Rev. D)

    Sathish

  • Hi Sathish,

     Thank you for your feedback.

    1.Can I control TPS650861 power off sequence through I2C? How to configure?

    2.When starting up, do the output ports of TPS650861 remain at low level output before the configuration is completed?

    3.What is the maximum current that BUCK1, BUCK2, and BUCK6 can output?

     Thank.

  • Hi Eric,

    Yes you can disable a rail thru I2C but generally powerup and power down sequence of the regulators and GPIOs are enabled by combination of CTL pins and PG signals. LDOA2 and LDOA3 are controlled only by I2C.

    TPS650861 should come with blank OTP. Since there are lot of registers and this is OTP (one time programmable 0 ->1) i recommend generating the script file from OTP generator and use IPG-UI for burning OTP. Of course if you want to write line by line I2C commands and the corresponding rail CTL pin is high then the output rail will be high as soon as I2C is written.

    Since these are controllers the maximum current depends on the external FET chosen. Please refer to the recommended FETs in the controller design procedure towards the end of the datasheet.

    Let me know if you have any other questions.

    Sathish