Other Parts Discussed in Thread: TPS650861, IPG-UI
Tool/software:
Hi team,
My customer is asking about the power-on sequence for TPS650864, which provides power rails for FPGA. The required timing sequence is as follows: BUCK1->BUCK2->BUCK6->BUCK3/BUCK5->LDOA2->SWB1_2->LDOA1->SWA1; How to configure? I have attached the TPS650864 schematics and the register settings, Please help to review that.. Thank you.