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Original question:

TPS61288: Maximum continuous current support

TPS61288: Issue with continuous and peak current draw of TPS61288

Mary Mbugua
Prodigy 10 points
Part Number: TPS61288

Tool/software:

I am using the TPS61288 to take in a variable input between 3.5- 4.5V at a max supply of 5A and intend to step it up to an output of either 5V, 9V or 12V; I expect a peak current draw of 2A for a 12V load. Basically I am trying to provide power to cellular routers with dual band support (have a higher spike current draw when registering to network; upto 2A at 12V); normal current draw is 0.55A at 12V once latched. The problem am observing is a voltage dip at output when the dual band router is setting up (suspecting the peak current when latching). Considering the chip is rated to output upto 15A (not sure at which voltage) am not sure where the problem is coming from. Also note that the inductor L1 I have used is rated 4.7uH and saturates at 24A. From the oscilloscope capture of the input, there is no dip at input when the output dips. Please note I have also added capacitor storage banks at the output of the TPS chip; I used a combination of 100nF ceramic capacitors (3), 10uF ceramic capacitors (3) and 22uF ceramic capacitors (4) and 100uF electrolytic capacitor with the smallest ceramic capacitor closest to the load for faster discharge during peak current draw and electrolytic capacitor placed further away but the dip persisted. Please also note though in initial design I had not added in the 30pF capacitor across R2 if greater than 15kilo ohms, I reworked the board to include it but the dip persisted.

  • 0
    TI__Genius 12335 points

    Hi Mary,

    Do you have a load current and SW node voltage waveforms?

    Please also double check that the COMP parameters are following the datasheet section 9.2.2.5 Loop Stability.

    Regards,

    Nathan

  • 0 in reply to Nathan Ding
    Prodigy 10 points

    Dear Nathan,
    Thank you for your feedback; I am not able to get the load current waveform however I will attach in the drive the current draw behavior as observed when using a power supply to provide input to the chip; current draw rises from an average of 0.4A to about 1.5A at dual band router start up, then at that capped current, the voltage dip happens. I will also attach SW waveforms at load and no load conditions; please could you help me make sense of the behavior of the TPS chip. For the COMP circuit, I have used the standard values as used on Figure 9-1. TPS61288 3.6-V to 13-V/2.3-A Output Converter; according to my research: Rc=36.5kΩ, Cc=1nF, Cp=30pF as used in my design provide:

      • Adequate phase margin (compensation zero ~4.3kHz)

      • High-frequency roll-off (pole ~145kHz)

        Kind Regards, 

        Mary.
  • 0 in reply to Mary Mbugua
    TI__Genius 12335 points

    Hi Mary,

    I understand that the COMP is used the value on Figure 9-1, but the BOM, mainly for the power inductor and output capacitor are different with the value in Figure 9-1, so the COMP parameters may need to be changed based on it. Not sure if you test the bode plot or not, a TPS61288 Design Calculation tool in ti.com can help you with the COMP parameters design.

    For the schematic and layout I don't see too big risk, so I think the TPS61288 should be ok to support the condition in your application if designing with proper compensation network.

    Regards,

    Nathan