TPS3431: TPS3431SDRBR

Sanjay Gadkari

Part Number: TPS3431

Tool/software:

Hi Team,

We are using TPS3431SDRBR Watchdog in our design as shown in the following diagram. The SET1 and WDI pins are controlled by CPU and the CWD pin generates 900 Milliseconds (max.) of Watchdog Timeout (tWD) with 10nF capacitor.

The WDO pin is connected to CPU reset pin POR_X, and SET1 pins is pulldown.

Test observation:

The WDT is enabled by making SET1 pin HIGH and WDI pulses are not applied, after 834ms WDO asserts LOW and CPU get reset hence watchdog disabled and due to this reset delay time (TRST) remains Low for 100us only.

Q1. With above configuration What is the minimum reset delay time (TRST).

Q2. Can it be less than 100us? (Like 1us or 10 us etc.)

Please refer attached file for details with waveforms.

TRST_Watchdog.docx

Regards,

Sanju

2 months ago

0 Jesse Villanueva 2 months ago

TI__Mastermind 18740 points

Hi Sanju,

For the TPS3431, you are able to truncate the WDO signal by pulling the EN pin LOW during WDO assertion. For example wire ORing EN and WDO. This will reduce the WDO pulse to ~200ns, EN to ENOUT delay.

Jesse

0 Sanjay Gadkari 2 months ago in reply to Jesse Villanueva

Prodigy 170 points

Hi Jesse,

Thank you for your reply,

But we are not pulling the EN pin LOW during WDO assertion.

We want the minimum time when WDO assert HIGH to LOW and LOW to HIGH (tRST), when SET1 pin transitions HIGH to LOW.(see below waveform)

Because when WDO assert Low, CPU get reset hence SET1 pin assert LOW and WDT gets disable.

Regards,

Sanju

0 Jesse Villanueva 2 months ago in reply to Sanjay Gadkari

TI__Mastermind 18740 points

Hi Sanju,

We unfortunately do not have the minimum value for this situation, we only have the typical value of 1us for the SET1 setup time. Yes the SET1 pin going low will also truncate WDO signal as well.