UCC14241-Q1: Suggestions to Optimize UCC21710 + UCC14241 SiC Gate Driver Implementation

Part Number: UCC14241-Q1
Other Parts Discussed in Thread: UCC21710,

Tool/software:

Hi,

This thread is A follow to this post on the forums:  UCC14241-Q1: RLIM Selection for UCC14241 for UCC21710 based SiC Gate Driver 

Based on the conversation from this previous thread, I am working a revised version of the gate driver implementation on the PCB.I have a few questions:

1. Can placing a zener diode for over-voltage protection from VDD-COM and COM-VEE adversely affect the functioning of UCC14241 in any way? I doubt it but just want to cover all my bases. Is there any other recommendation for OVP beyond zener diodes? I currently have only one zener as overvoltage protection across gate to kelvin source, but I'm a bit concerned that this alone is insufficient.

2. Apart from populating the RDR circuit, are there any suggestions on capacitor selection? Here are the values I am using for +15V/-5V voltage rails based on the excel calculator: Cout1 = 10 uF, Cout1b = 2.2 uF, Cout2 = 1 uF; Cout3 = 3.3uF; Note: Cout1b, Cout2 and Cout3 are placed as close as possible to UCC21710 pins. Will changing Cout1b to 10 uF help or hurt in terms of ripple observed on Vg-ks?

3. Would there be any other suggestions apart from layout guidelines included in the datasheet?

Thank you for any advice that you might be able to share.

    1. Can placing a zener diode for over-voltage protection from VDD-COM and COM-VEE adversely affect the functioning of UCC14241 in any way? I doubt it but just want to cover all my bases. Is there any other recommendation for OVP beyond zener diodes? I currently have only one zener as overvoltage protection across gate to kelvin source, but I'm a bit concerned that this alone is insufficient.
      1. Many TI customers using UCC14241-Q1 and it is not common to add zener diodes tot eh output(s). This is common practice when the outputs of a bias supply regulator are not regulated and need post regulation. UCC14241 has output OVP/UVP protection that is active whenever FBVDD or FBVEE are more than ±10% from 2.5V. Way more accurate compared to a Zener. Are you trying to protect from OVP to less than the 10% you are already receiving from UCC14241 OVP?
    2. Apart from populating the RDR circuit, are there any suggestions on capacitor selection? Here are the values I am using for +15V/-5V voltage rails based on the excel calculator: Cout1 = 10 uF, Cout1b = 2.2 uF, Cout2 = 1 uF; Cout3 = 3.3uF; Note: Cout1b, Cout2 and Cout3 are placed as close as possible to UCC21710 pins. Will changing Cout1b to 10 uF help or hurt in terms of ripple observed on Vg-ks?
      1. Any and all split capacitor outputs that are commonly used on transformer driver circuits as well as UCC14241 are operating on the principle of charge balance where C_VDD*VDD=C_VEE*VEE. The Excel takes additional factors into account such as: gate driver quiescent current and any additional quiescent load current required from VDD or VEE. If you deviate away from the "ideal" capacitor ratio, you risk violating charge balance. RLIM can help compensate for small charge imbalance but only up to a point. RDR help extend the RLIM ability to compensate over a wider range while maintaining low UCC14241 power dissipation.
    3. Would there be any other suggestions apart from layout guidelines included in the datasheet?
      1. The PCB layout guidelines in section 12.5 of the UCC14241 data sheet and the EVM User Guide are the best PCB design resources. The UCC14241 Excel Design Tool is the best design reference for optimizing the capacitors and RLIM configuration.

    Regards,

    Steve