• State
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 159 views
  • Users 0 members are here
Support feedback
Options
Options
Related

Original question:

BQ76952: DFETOFF pin configuration problem

BQ76942: DFETOFF pin not turning the Discharge FET ON in parallel FET configuration

Vinayak D
Prodigy 10 points
Part Number: BQ76942
Other Parts Discussed in Thread: BQSTUDIO

Tool/software:

Hello,

I'm trying to turn the Discharge FET ON through DFETOFF pin but unable to do so. Just for context, the FETs are in parallel and there is no microcontroller in this design so the FET control should happen from the device itself.

I've checked other things such as voltage readings, protections through BQStudio and they are working fine.

As described in the note here, the DFETOFF Pin Config should be 02 same as CFETOFF Pin Config.

Also according to the discussion here, FETs will be turned on when DFETOFF pin is pulled to GND. On the DFETOFF pin, I'm using an external resistor to pull it up to 3.3V.

The discharge path section from my schematic is shown below 

Please let me know if any further details such as particular section details are needed.

Regards

  • 0
    TI__Prodigy 730 points
    Vinayak D said:
    FETs will be turned on when DFETOFF pin is pulled to GND. On the DFETOFF pin, I'm using an external resistor to pull it up to 3.3V.

    So, you are using an external resistor to pull the pin to logic High. How is the pin pulled to GND, in order to turn the FETs ON? Is it left floating?
    Also what is the value of the external pull-up resistor?

    DSG FET, when asserted. When the DFETOFF pin is de-asserted, the DSG FET will only be enabled if there are no other items blocking them being re-enabled. Can we confirm there are no other conditions blocking the DSG FET from being re-enabled?

  • 0 in reply to Gavin Long
    Prodigy 10 points

    Hey Gavin,

    We are using a 10K pull up resistor to pull it up to REG1 which is giving out 3.3V and using a switch to pull it down to GND, this is verified using meter. Should we try giving it to 3.3V from a different point ?

    Also, sharing a screenshot from BQStudio which shows there are no protections being triggered, if you can let me know any specific conditions other than these protections that are needed to be checked as the DSG pin is not changing and is latched to high all the time and consequently we are not able to turn the discharge FET ON or OFF.

    So just to make clear, DFETOFF pin functionality is not working whether it is turning ON or turning OFF the FETs, as Settings:Manufacturing:Mfg Status Init[FET_EN] is set during OTP so the FETs are always ON.

    Thanks

  • 0 in reply to Vinayak D
    TI__Prodigy 730 points

    1. I don't see anything wrong with the status & settings visible from the BQStudio screenshot you shared. 
    Can you confirm the Register Settings:FET:FET Options[SFET] ?
    From the TRM it states: "The Settings:FET:FET Options[SFET] configuration bit should be set when FETs are used in a series configuration, and should be cleared if FETs are used in a parallel configuration. If the system will only use a single FET (such as a CHG FET with no DSG FET), the device can be configured for parallel configuration with the DFETF Permanent Fail disabled."

    It's possible in series configuration the device is automatically forcing the FET on, to prevent body diode conduction and damage.

    2. Can you provide the full list of register settings in file format to assist in fully debugging your issue?

    3. In addition, it may be helpful to provide the full schematic to confirm there are connection issues