LMG2100R044: HS min on-time

Hi ,

There is no straightforward answer for the high-side minimum on-time as it is very application-dependent. 

The main item that should be insured is keeping the HS-HB voltage above the device's UVLO turn-off threshold (3.7V maximum) to prevent it from shutting down. 

To ensure that this voltage remains at an acceptable level, the simple capacitor voltage-current relationship can be used: i = C * dv/dt.
In this equation,
-i is current consumption of the high-side device.3.5mA can be used here.
-dv is the voltage droop in the capacitor when the high-side is on.
-dt is the time that the high-side is on.
-C is the bootstrap capacitor value. 

C should be designed such that the voltage droop (dv) does not fall below the maximum UVLO turn-off threshold and with some additional margin.

As an example, let's take the case of a buck converter operating at 500kHz with an 80% duty cycle on the high side. Here the period is 1/500kHz =2us and the high-side on-time is 80%*2us = 1.6us. Assuming the VCC voltage is 5V, the bootstrap capacitor will get charged to Vboot = VCC - Vdiode = 5V - 0.9V = 4.1V

Then, when the high-side is on for 1.6us, the capacitor voltage droops according to Vdroop = dv = i/C*dt. 

Now, we design for the value of the bootstrap capacitor - if I want to keep Vboot above 3.7V, say about 3.9V, Vdroop must be equal to 0.2V.

Therefore I can rearrange the equation above to solve for C: C = i*dt/dv= 3.5mA*1.6us/0.2V=28nF.

Thanks,

John