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Original question:

TPSM8287A06: Remote sense to the other board

TPSM8287A06: remote sense routing guide

Tim Peng
Prodigy 150 points
Part Number: TPSM8287A06

Tool/software:

Hi Support 

in section 7.3.15 remote sense of TPSM8287A06 datasheet, it says "These sense lines must be routed in parallel and away from noisy signals. Connect them to the lowest impedance point on the output bus, which must be the center of the output capacitor bank closest to the load."  

I have a few questions: 

(1) what exactly does " the lowest impedance point on the output bus",

is there any concrete example or application note? 

(2) what does it mean "sense lines must be routed in parallel"? 

Is there any trace width and spacing requirement? Or how to calculate ? I'd like to confirm that we don't need to control their impedance, unlike with signal traces.

  • 0
    TI__Guru**** 150930 points

    Hi,

    In many cases when powering a processor, the output plane impedance is analyzed as a PDN.  Usually, some maximum impedance is allowed by the processor.  For best AC response, the device should sense the voltage at the lowest impedance spot on the output.  This should also be where the load's decoupling caps are located.

    The sense lines should just be routed together, side by side (in parallel) to the load and away from aggressor signals.  There is no impedance matching requirement for them.

    You can see the EVM layout for an example: https://www.ti.com/tool/TPSM8287A06BASEVM The gerbers are available there as well.

    Thanks,

    Chris

  • 0 in reply to Chris Glaser
    Prodigy 150 points

    Hi Chris, a few more questions:

    (1) In your reply "The sense lines should just be routed together, side by side (in parallel) to the load and away from aggressor signals.  There is no impedance matching requirement for them.". I am wondering if it is better to route sense lines as wider as possible since we need a lower-resistance sense path, could you help to answer this assumption? 

    (2) I often hear that the shorter the remote sense traces, the better in some other guide. Do remote sensing wire runs have length limitations?

    (3) some guides (like Remote sensing for power supplies, published by TI)  indicate "A high frequency bypass capacitor (CBypass) can easily remedy the situation. It filters out the high frequency dynamic voltage while keeping the characteristics of DC remote sensing. could you also where to add this capacitor exactly? Is it placed between Vout and negative sense node and in proximity to regulator?

  • +1 in reply to Tim Peng
    TI__Guru**** 150930 points

    Hi,

    1) No, thin, signal traces are fine.  The sense traces do not need to have low resistance, as there is not high current flowing in them.

    2) There is no length limit, but it is always better to place the DC/DC close to the load.  This reduces the impedance between the DC/DC and the load, which usually improves transient response.  And it is usually more efficient, since a buck converter's output current is higher than the input current, so the output plane resistance has higher losses than the input plane.

    3) I think you mean this app note? https://www.ti.com/lit/an/slyt467/slyt467.pdf In that one, Cbypass is used for the device which does NOT have remote sense.  There, Cbypass is placed between the Vout plane (near the IC) and the separate Vout trace (which implements a remote sense function).

    Chris

  • 0 in reply to Chris Glaser
    Prodigy 150 points

    Thanks for replying, Chris.