TPS4816-Q1: TPS48161 asserts FLT pin when INP_G is driven high with small loads

Hello, 

Can you please provide a schematic? 

Looking at your first scope shot I'm concerned that both of your gates appear to be driven high when INP_G is high. Per your labels CH4 should remain low during this time if INP (Ch2) is LOW. 

Thanks, 

Sarah

Sarah,

Here is a partial schematic which covers all the TPS48161 circuitry.

I am confused by your comment as the first scope shot shows G going high (Vout+~10V) when INP_G is high and GATE going high (Vout+~10V) when INP is high. You can see the ripple from the charge pump. Vout+~10V means the VGS of the mosfets should be sufficient to turn them on only when their respective controlling inputs are high. This is what I would expect. When the controlling inputs are low, the gates are at Vout but not above it.

6758.Schematic for TI.pdf

My main concern is the FLT output shown in screen cap 2-4 asserting (low) for some reason.

Hi Sarah,

I have a lead on the issue. This excerpt is from page 19 of the dtasheet:

I have measured this Vbypass scp voltage and found I get spikes on it before FLT asserts low

.

Input 1: FLT, Input 2: DRN, Input 3: CS2-, Input 4: INP_G MATH: DRN-CS2-

Here we can see around the time INP_G goes low and FLT asserts low, there is a spike on the MATH trace (DRN-CS2-) that goes up to several volts, certainly above the 2V threshold.

If we zoom in on the time scale, we get the capture below

Input 1: FLT, Input 2: DRN, Input 3: CS2-, Input 4: INP_G MATH: DRN-CS2- (1V per division)

We can see that INP_G (4) goes high first, then we get the spike on the MATH trace (DRN-CS2-) that goes up to ~3 volts, then FLT (1) asserts (low).

I have the recommended filtering on DRN (see section 9-3 of the data sheet) but I have removed it in the capture above to make the filtering on DRN and CS2- more similar to try and reduce the spike. I assume I would need to add similar filtering on CS2- but that will be very difficult on my PCB as I have not allowed footprints for it.

Am I correct in this line of thinking?

James

Hi James, 

You labeled the Ch2 as INP. In this waveform both G and GATE are high, while INP is low. Gate should not be high here. 

For the above it seems like you might now be pre charging correctly. You have an RBypass = 12 ohms which seems high for 2A --> This would be closer to 1 ohm.

We do not typically recommend filtering on CS2- and this does not look like noise as much as improper pre charging. Your voltage drop is too high across the bypass resistor indicating you have more current than expected.

Thanks, 

Sarah

Sarah,

I went through the section on specifying Rbypass again and revised my value down to 1 Ohm initially then down further to 0.5 Ohms. Combined with adding an Rg and Cg to ground onto the bypass FET gate, I can now control the soft start properly in that I can set the risetime of the output voltage for a known capacitive load. See below  

Input 1: INP_G, Input 2: FLT, Input 4 Vout. Load is 22 Ohms in parallel with 4 x 220uF electrolytics.

As I decreased Rbypass and Cg, the ramp on the output got steeper as I would expect.

I still cannot start my electronic load (BK Precision 8510B) even with it set to 0.1A.  If I start the circuit first then turn the load on, it is fine.

Most importantly, I still cannot start my application load. 

I'm assuming I still need more soft start current available? 

Hi James, 

Are you using the eload in CC mode? I would recommend using CR or a real power resistor. Staring your circuit first and then applying the load working makes me think you could be pulling a much heavier load than expected with CC in the start up. You can also monitor your input voltage to see if there is evidence of supply droop as a result. 

What is the difference between your application load and the eload? 

Thanks,

Sarah