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Original question:

TPS650864: PMIC sets Temp_Crit during power up sequence and restarts

TPS650864: maximum allowed capacitance on buck 3/4/5

eric Kuin
Intellectual 430 points
Part Number: TPS650864

Tool/software:

Hi, 

I am using the TPS650864 to power a AMD Kintex FPGA. There is a power-up issue that results in an emergency shutdown and sets the Critital Temperature bits in the registers. the PMIC starts up again and retries for 10...100 times in a row (hiccuping) before a stable power on is reached.
After some testing I found out it is the capacitive load during ramping up of the 1V8 that causes the shutdown. When I lower the number of capacitors the PMIC starts up normal.
See the linked thread that I posted before, but that one is closed without an answer or solution.

In the datasheet there is no mention of any maximum value to be used on the buck 3/4/5 converters.

It would help if there is a guidance to determine the safe value of maximum capacitance and some details how to measure the margins.

Thanks

  • 0
    TI__Genius 10467 points

    Hi Eric, 

    Thank you for the update, I am glad you were able to identify the issue. 
    This is a known issue that too much capacitance can cause a fault issue. Maximum capacitance should not exceed 400 uF, this may vary with the exact VOUT values.
    The high inrush current is causing the fault. We recommend lowering the capacitance.

    May I know the exact capacitance value you were using on this rail?

    I'll see if we can update the datasheet so this maximum capacitance is more clear. 

    Generally, above 200 uF C_out does not see much of a difference in performance, so we typically recommend < 200 uF, with 400 being the maximum:

    Relevant thread:  TPS650861: FIrst voltage rails do not start properly 

    Best Regards, 
    Sarah

  • +1
    Intellectual 430 points

    Hello Sarah,

    in the design there were 2x100uF MLCC at the output of the buck 3/4/5. For this 1.8V rail there are near the FPGA 3 times a 100uF for the multiple power planes and some 10u+4.7u local caps.

    The TPS650864 datasheet calculation shows that 2x22uF at its output is sufficient.
    For the FPGA power planes I will lower the 100uF to 47uF and keep the 10u+4.7u as described in FPGA user guide. 
    This will have a total capacity around 260uF.

    This should fulfill the values you mentioned (<400uF), follow the recommended values in datasheet and UG, and have commonality in capacitor values/types in my BoM
    I will check the other rails too and lower the values where required.

    I have a last questions about this issue: why is Temp_Crit flag set due to this high capacitive load.?


    Thanks for this answer.