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TLC5970 Grayscaling and register problem with differential interface

Christian Voglhuber
Prodigy 60 points

Hi,

we would like to drive the TLC5970 PWM LED Driver with dc/dc and differential interface from our ARM microcontroller (plus differential drivcer ic) but some Grayscaling register data is not working.

As described in the datasheet we send the FC (function control) data (1111 0000 0000 0000 0000 0000 0000 0001 1111 1111). This function data looks like it's working. The device is in auto repeat mode.

The real problem is the grayscaling register, beginning address 0000.

If we send the bitstream 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 all LEDs are bright, but if there is no 1 in the first 7 (header and 3 data) bits no LED is lighting.

In our test setup there are 2 ICs in series. If we send 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 (for the first ic) and 0000 0000 0000 0001 1111 1111 1111 1111 1111 1111 for the second IC no output is correct. It doesn't matter where the bitstream with no 1 in the first 7 bits occures (in each of the 40 bit data streams).

Our sending function looks like this:

  • Clock low
  • Desired data bit
  • Clock high
  • Clock low
  • Desired data bit
  • ......

Comments are highly appreciated.

  • 0
    TI__Intellectual 980 points

    Hello Christian-san,

    Could you let me know more detail?

    Q1;Is a following issue only cascading(two ICs) or one IC also have same issue? 

    >>If we send the bitstream 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 all LEDs are bright, but if there is no 1 in the first 7 (header and 3 data) bits no LED is >>lighting.

    If you send data "0000 0000 0000 0001 1111 1111 1111 1111 1111 1111"  for 1sr IC and next send data "0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 " for 2nd IC,is it same issue?

    If it's so,it may be internal latch error.

    Q2; What data did you write to Internal latch pulse delay time in EEPROM?

    Please look at an attaching file.

    1106.TLC5970cascadel.pdf

    Internal latch pulse happen at the latch delay time in EEPROM after stopping CLK automatically.

    If CLK to CLK is longer than the latch delay time which is set in EEPROM or between 40bits data and  40bits data is also longer than the delay time,

    data is not generated correctly.

    Could you please check it on your program?

    Best Regards

    K.Narisawa

     

     

     

     

  • 0 in reply to Kiyoshi Narisawa
    Prodigy 60 points

    Hello K.Narisawa,

    Thank you for your reply.

    Q1;Is a following issue only cascading(two ICs) or one IC also have same issue?

    For one IC it's the same error.

    If you send data "0000 0000 0000 0001 1111 1111 1111 1111 1111 1111"  for 1sr IC and next send data "0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 " for 2nd IC,is it same issue?

    Yes, it's the same issue.

    Q2; What data did you write to Internal latch pulse delay time in EEPROM?

    Internal latch time is standard, so it's around 16ms delay and our programm makes after the 80bit, for the 2 ICs 100ms delay (there is no delay between the two 40bit blocks). We only changed the dc dc ph duty in the eeprom to 10.2V for our 3 LEDs in series.

    Thank you for your help.

  • 0 in reply to Christian Voglhuber
    TI__Intellectual 980 points

    Hello Cristian-san,

    Thank you for your reply.

    It seems communication error. 

    Could you let me know wire length between IC to IC for differential?

    If IC to IC is long distance, it needs termination resistor of 102ohm on DATA+/- and CLK +/-.

    This is on application note on below URL. 

    http://www.ti.com/lit/an/sbva036/sbva036.pdf

    If you can send photo and schematic,it's helpful for me.

    Best Regards

    K.Narisawa