UCC39002 Oscillation

Lance Collins

Other Parts Discussed in Thread: UCC39002, UCC29002

I am using the UCC39002 current share control IC for a 2N redundant 5V at 16A application using DC-DC modules. The modules have a COMP output pin that is proportional to the output current. I am using this COMP signal as the input to the Current Sense Amp. At full load, COMP=1.35V. The gain of the CSA is three (specified minimum in the data sheet), so the CSO max = 4.05V at full load.

The issue I am having is that there is an oscillation on the ADJ line at startup. The UCC39002 specification states that the CSA is not unity gain stable, and must have a minimum gain of three. I am wondering if perhaps I am encountering the instability because the CSA is right at the lower limit of the gain spec. The oscillation looks like a relaxation oscillator and not a sinusoidal oscillation. Can anyone explain what is happening and why I'm getting an oscillation at startup? Does this oscillation look characteristic of the oscillation that might appear under unity gain? The problem only appears at startup and normal steady state operation and transient load operation all look good.

6712.5V0_SSD Current Share 2N Startup Showing Oscillation.pdf

2475.JSC Schematic Current Share.pdf

thanks,

Lance

over 12 years ago

0 Lance Collins over 12 years ago

Intellectual 535 points

I have included the zoomed out picture of the startup to help see what is going on.

2480.5V0_SSD Current Share 2N Startup Showing Oscillation 2.pdf

0 Antenna_Head over 12 years ago in reply to Lance Collins

TI__Genius 12690 points

Team-

Please review and respond to this issue, thanks!

Best, steve

0 Lance Collins over 12 years ago in reply to Antenna_Head

Intellectual 535 points

The sudden maximum ADJ adjustment looks like the UCC39002 on side 1 is cyclically entering and exiting the startup state. The data sheet does not describe in detail how startup is defined and the conditions for entering and exiting the startup mode. Can anyone give a better description of the conditions for determining the startup state? Is there a timer off of the internal BIAS OK signal? The original design had VDD=5V which is fairly close to the BIAS OK threshold of 4.575V, but reworking VDD=12V did not fix the oscillation problem.

I'm also seeing an oscillation on side 1 when side 0 is hot plugged. Again, I believe that startup mode is entering and exiting when it should not be. I have ordered the UCC29002 which does not have the maximum adjustment at startup feature as I do not need fast current sharing at startup.

0 Lance Collins over 12 years ago in reply to Lance Collins

Intellectual 535 points

The UCC29002 did not eliminate the oscillations. The exact same performance was observed.

Using the UCC39002 EVM I built up a controlled test setup. The EVM was populated with parts as in the attached schematic. Note that circuit 1 used 5-Ohms (two 10-Ohms in parallel) for R-sense and circuit 3 used 10-Ohms . In this way I could make circuit 3 appear to drive more current. The test setup was run open loop with a bench supply connected to V-in1 and V-in3. The ADJ pins were pulled up with 24.9-Ohm to the common output local sense, but there was no feedback to force any kind of current sharing. V-in3 turn on was delayed with the use of a series 3-Ohm resistor and 3x6800uF caps. The normal startup would force circuit 1to be the master until the 3x6800uF caps charged up and then circuit 3 would become master. In this manner I could observe how the UCC39002 controllers could handle the transition.

At turn on, I discovered a "blip" in the adjustment, but no oscillation.The blip appears on U3-EAO as the level decays from ~3.76V (saturated) down to near zero. U1-CSO is the master and is driving LS at this time, so U3-EAO should be rising (or in this case remain saturated). When U3-EAO hits zero Volts, then there is a step in ADJ from maximum adjustment to no adjustment. The operation of ADJ should be linear and there should be no abrupt step changes. If EAO is gradually going low, then the adjustment should also be gradually going low with no abrupt step. As U3-EAO slowly rises following the step change, ADJ adjusts as expected in a linear fashion. This step and recovery is exactly what I'm seeing in my application, except in the application the blips keep on repeating until finally dying out. I want to make sure that I never have a situation where the blips repeat forever and never die out. Can anyone explain why this blip is occurring?

An additional observation - The datasheet describes a startup state that drives maximum adjustment at startup. Startup is not defined, but I was not able to create the maximum adjustment with Vin =5.0V steady state and turning on external bias. Since there was already current flowing from the steady state operation, the master is circuit 3 and when bias is applied there is no adjustment made; circuit 3 continues to be the master with no adjustment. What is the definition of startup if it's not application of bias power to VDD?

5482.UCC39002 EVM Test Setup Schematic.pdf

zoom in on "blip"

0 Lisa Dinwoodie over 12 years ago in reply to Lance Collins

TI__Genius 15910 points

Are you using the UCC29002/1 version of the load share controller? The non-/1 versions are designed to rail the ADJ amp at start up, the /1 version starts up in a more linear manner. Railing the ADJ amp at start up helps to jump start the control loop but usually results in oscillation, the /1 version is slower at start up but is much softer and gentler and usually takes away the oscillation.

Note that load share is only effective at steady state and any transient, such as load step, turn on, turn off of modules, will result in a brief period of oscillation due to the required slow loop response. Depending upon the bandwidth, this oscillation could be in excess of 100ms or so before the master/slave relationship is established and load share is steady.