Question about UCC28600 Excel Calculator

No, please do not try to design the power stage of the UCC28600 (primarily the inductor value) so that the switching frequency at high load, low line, is forced to switch at a lower frequency.  The design calculator has been specifically revised so that the minimum switching frequency when loaded and at minimum input will not go below 80kHz, at least in the calculations for nominal component values so that there is enough margin to avoid triggering a fault response and turn on issues over device tolerances, part to part variations, and temperature range.

By forcing the converter to switch at this higher frequency when the on-time would be required to be greatest (high load, low input) it achieves the desired result of limiting the on-time of the controller to a target of less than approximately 6.8us.  This is because the on-time must be forced to be less than an internal signal (QR_DONE) that is designed to blank out any percieved valley that would be erroneously interpretted as a signal to initiate another switching cycle.  If the on-time is long enough to overide this blanking time, the controller will enter into a fault mode and you would have start up issues load.  Designing the power stage to maintain a switching frequency at a target of 80kHz minimum (so that  etc. keep the on-time less than the QR_DONE blanking signal) will avoid these issues. 

Hi, Lisa

Thank you for your comment.

Could I ask you a few more questions as follows?

1. If the on-time is long enough to overide the blanking time(approximately 6.8us) that is determined by QR_DONE signal,

   Which fault  will be detected by UCC28600 (descrived in Figure 8 Fault logic details)?

2. Could you tell me about your comment  "start up issues load" in a little more detail?

Regards,

Go

I meant to say "start up issues under load" as the result of the extra pulse will result in a CS signal that exceeds the programmed peak current limit and will detect an over-current fault.  Under no load conditions, the over-current fault is a non-issue.

Thank you for detailed comment.

Do you have any other QUASI-RESONANT FLYBACK CONTROLLER that can set the minimum swithching frequency

under 80KHz?

Go

What is the power level of the application?  The UCC28610 may be a suitable option. 

Here is the power level customer's application.(please see the attached excel file)

At this condition, the on-time of UCC28600 will exceed 6.8us with the primary inductance value that decide by the culculator

 at low input voltage, is it no problem? or we need to change the inductor value to lower ?

And I have additional question about UCC28600 65-W Evaluation Module,

Do you have any document about the spec of the transformer(GCI G065022LF)?

I couldn't find any information about G065022LF at GCI's website.

Thanks,

Go

In regards to the attached calculator:

first of all, do they really want to trigger the output over voltage protection at 28V for a 12V output?  This will directly affect the resistor values on OVP and have an effect on the converter operation.

second: are you sure they will use the required input capacitor to maintain an input voltage ripple of 5%?  Quick calculation shows that's about 1000uF.  The minimum bulk voltage is an important design parameter as the entire power stage (ie inductance) is designed based upon peak current and maximum on-time at this minimum input voltage level. A voltage ripple of 20% might be a little more reasonable as it would require a 220uF input capacitor.

Admittedly the spreadsheet is not ideal and does expect the user to "massage" the design once you get to the QR simulator page.  I would recommend using a lower inductor and also use the recommended values for the OVP, power limit and current sense resistors for the lower inducatnce level, for a robust and reliable design.

The OVP setting value(28V) was wrong, the customer set it 15V actually.

and there is the PFC circuit before UCC28600, and the PFC cuircuit has 1000uF output cap.

So regardless of the PFC circuit condition(means ON or OFF), input voltage of UCC28600 will keep the ripple within 5%, the customer said. 

Sorry for asking so many questions, please let me know about the following things.

1.  Regarding your comment "an effect on the converter operation",

     Does it mean that It will give some effect on the normal operation of UCC28600?

2. Regarding the attached calculator,

    I think the ton value has enough margin under the condtion see in the attached calculator,

   Can't we set the minimum Switching frequency to lower in this condtion?

3. Regarding the UCC28600EVM-65W,

    Do you have any data for multiple output operation? (especially the cross-regulation of each output)

Thanks,

Go

1. The output OVP set point will impact the resistor values used on the divider.  These same resistors are also used to set the the internal current used in power limit (works with the Rpl), and sets line OVP so thresholds and operating points will be influenced by these resistors.  I just wanted you to be aware that this output OVP value determines the value of the resistors which has an impact on the other components in the circuit to get the desired results.

2. The QR simulator page is where the user takes the recommended compnent values from the QR design tool page and can modify the inductance, the turns ratios, the Rcs, Rpl, and Rovp resistors to massage the design for the desired result.  Yes, you can modify the  values here to reduce the switching frequency (usually by increasing the inductance first and then using the recommended resistors and turns ratios).  The QR design tool sheet will recommend what is theoretically optimum but the user can modify at will and change at their own risk, perhaps optimizing the design to meet their own specifications.  I do recommend that if the end result of the user's changes don not function as intended, test with the recommended values in the application just to confirm that the changes made did not result in any unintended consequences.

3. The EVM was originally intended for multiple outputs and can theoretically do this but it should be noted that slave outputs were difficult to support at burst mode and light load.  Cross regulation of the outputs is dependent upon the coupled inductance and output load.  Lightly loaded slave windings will tend to have higher output voltages when the main output is heavily loaded.  Multiple windings would tend to make really good coupling a challenge.  In frequency fold-back mode, the on time and peak current is maintained but the switching frequency is modulated.  During this mode of operation the regulation of slave outputs is sacrificed because the switching period is increasing with a constant on-time and also a constant demagnetizing time (the time the output rectifiers conduct).  The increasing switching period but constant demag time means a drop in overall demag duty cycle which will cause decreased output voltages on the slaves, including the bias winding when compared to their values at full load.  Most multiple output flybacks would use a linear regulator on the slave outputs for good regulation, unfortunately during burst mode there may not be enough bias to keep the linear regulator going (loss of headroom).  you could add a minimum load to the converter to avoid burst operation but then you will not have very good no-load power consumption results.