Full-Load to Short-Circuit transient response of TPS2553

See datasheet: Fig 3, Fig 4,  Fig 20.  Experimental short circuit waveforms and response are very sensitive to the the test setup including input capacitance/voltage/impedance, output capacitance, load (short) impedance), device temperature, current limit program point, etc.   In this case, the input voltage experiences a big droop (to 1 - 2V), indicating a lot of impedance. 

The input voltage overshoot (as the current drops, V = L x dI/dt) implies insufficient close-up low impedance capacitance, and  most likely excessive input inductance.  The inductance is sometimes the result of testing an EVM board with long input leads and other undesirable practices.  The input voltage absolute maximum rating is grossly exceeded.  The input overshoot is just the physics of energy storred in the input circuit inductance (1/2 x L x I^2) discharging into the downstream load (e.g. capacitance).

In a similar vein, the output undershoot is the result of energy storred in the output circuit inductance discharging into the upstream load (capacitance and the IC).  I have seen this before and consider this "normal." 

Dear Martin-San,

Thank you for your kindly response. Let me confirm it by addition.

You say that "In this case, the input voltage experiences a big droop (to 1 - 2V), indicating a lot of impedance",

but, this IC's absolute maximum rating are -0.3V to 7V from datasheet.

Does not this device destroy it if I input  from -1V  to -2V?

Are there the countermeasures to prevent some destruction?

Perhaps we had a miscommunication.  I was pointing out that the input voltage went to a value between +1V and +2V.  I had used to "-" to indicate "to."  Note that the current limit speed might have been slowed as the part hit its UVLO.

Dear Martin-San,

Thank you very much for right indication. I understood input voltage

About the output voltage, is there the countermeasure to prevent the Vout drop (-1V), just after the short circuit?

Is the capacitance value change of an input capacitor (0.1μF) and the output capacitor (120μF) effective?

Because Vout becomes -1V, does not the destruction happen to the output block of this IC?

Generally speaking, both issues can be controled with appropriate input and output capacitance.  Input capacitance depends on teh circuit and layout design.  Output capacitance should probably be no less than 10uF to control the undershoot, but need not be as high as 120uF.  The type of capacitance (low ESR) is important as well.

Dear Martin-San,

Thank you. I understood the recommendation of the output capacitor due to your answer.

But, we think that it is difficult to completely suppress the drop of the output voltage (-1V).

Therefore, please teach whether we do not have to worry that this IC is destroyed by drop of the output voltage (-1V).

Our customer worries whether this IC is not broken for output voltage drop (-1.0V).