LM5070 PoE PD_3.3V schematic review?

I would route the GND and SGND "areas" as separate sections and then tie GND and SGND together with a section of trace (maybe 100 mil width or so). This way, they are at the same potential but circulating currents on primary and secondary side are localized.

Hi Eric wright,

Thank you very much..

But l could not understand 100% ,

So If you have,

Would you please let me know the PCB Layout data by picture?

Thank you,

Eric

You can refer to TPS23753AEVM-001 user guide (http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slvu315&fileType=pdf), figure 9. The left side of the mirror PCB plot is secondary and the GREY fill is SGND. The middle section GREY fill is GND. Now zoom in on C1 which bridges the isolation barrier for this "similar" EVM type. My recommendation would be to replace C1 with a zero ohm resistor (or a piece of trace between the pads) in a non-isolated application.

I've a question for TPS23750 of POE.

In case of Surge TEST 1kV(1.2us/50us) combination wave,

TPS23750 is died by surge damage,

Test condition is input DC 48V at that time,,

How about addition VARISTOR between bridge diode(AC+) and (AC-) in order to protection the surge damage,

( VARISTOR : 275V RMS 7MM RADIAL)

Could you please review the attached schematic and guide your sloution asap?

6283.poe_Board_20130612-.pdf

Thanks...

eric.

Make sure the SMAJ58 TVS and 0.1uF cap are very close to TPS23xxx (or LM50xx per post title) Vdd and Vss pins and are connected with low inductance copper.