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BQ77PL900 Shutdown

Travis Pollok
Prodigy 110 points

Other Parts Discussed in Thread: BQ77PL900

So there's some confusion when I'm reading the datasheet for the BQ77PL900 battery protector on how to commence shutdown.  In both cases you have to be in Host Control mode I get that but page 9 says to shut off the DSG FET and then send the shutdown command and page 38 says to just send the shutdown command.  So which way is the correct way so I don't end up with a protection circuit still in normal mode until the batteries drain?

And any help on the best way to code this would be great.  I'm attempting to use an Arduino Uno and the Arduino IDE to send the commands.  It's what we've used before when initially programming the UV and OV for the protector but the process of doing that was detailed step by step on page 37.  Help?

  • 0
    TI__Guru 54715 points

    To enter shutdown the PACK pin voltage must drop below the wake threshold. Normally with a circuit like the simple system diagram around the block diagram of page 6, you will need to turn off the DSG output.

    On page 38 in the Shutdown Mode description for the host-control mode "... the DSG FET is turned OFF..." is an action which must be taken by the host.  You can set the DSG off first or set the SHDN bit first.  The part will stay on until PACK pin falls sufficiently.

  • 0 in reply to WM5295
    Prodigy 110 points

    To turn off the DSG FET would the it be sending it to address 0x01 with 00000100?  So that FS stays at default, PFALT stays at default, GPOD stays at default, CHG is ON, DSG is OFF, and LTCLR isn't toggled?  Just the CHG and LTCLR are in question with that.

    And when sending the shutdown command bit, do you send it with the host control bit on still as well? So to 0x01 is it 00000001 or 00000011?  Sorry if these are obvious answers, but I'd rather get it right before I start running anything.

  • 0 in reply to Travis Pollok
    TI__Guru 54715 points

    When you write, you write all bits in the register which are not read only.  To change a single bit you will likely want to read the register, modify the bit and set it back.  If you remember the state you had you could modify that value and write the register.  If you are just setting a new state, you may not care what the previous value was and just write the desired value.

    For example if you want to shut down, you might just write register 1 to 0x00 to turn off all FETs and use the longer sampling delay (FS = 0).  Or if you were using FS = 1, you may want to write 0x80.  Then write the shutdown bit in register 2.  Here you want to stay in host mode so that it will shut down, so you would want to write 0x03, or you may want to keep your VGAIN and IGAIN settings even though you are turning off  the part and they will go away when shut down is complete.

  • 0 in reply to WM5295
    Prodigy 60 points

    Hello,

    I have a question about Shutdown.   I'm discovering that I have a residual 3.2 volts on the PACK pin that is coming from the chip internally.    My 100k resistor can't seem to pull it down to zero in order for the BQx to shutdown.    Can anyone tell me what would keep PACK high?    Is there a tie internally to anther pin that could be causing it?

    Todd

  • 0 in reply to Todd Petersen
    TI__Guru 54715 points

    Be sure your discharge FET is turning off completely if you have the conventional circuit.

    There is a diode from CHG to PACK.  See http://e2e.ti.com/support/power_management/battery_management/w/design_notes/faq-bq77pl900-fet-drive-information.aspx  So a residual voltage on the pack+ net even if you pull down on PACK won't  necessarily take it low due to the gate resistors and internal diode from CHG to PACK pin. 

    If you have a non-conventional circuit and want to switch PACK off with a residual voltage on the pack+ net, you will need to switch CHG also.

     

  • 0 in reply to WM5295
    Prodigy 60 points

    Thank you for the reply on a Saturday night... this is really helpful.    Based on that, I think I have some resistors mis-sized, or maybe too many.   Any suggestions?

    5355.drive.tiff

  • 0 in reply to Todd Petersen
    Prodigy 60 points

    By the way... VGATE is a 9v charge pump driven by the uC.    I believe it's what's providing the 0.3v feedback.   I can shut it down, but I'm now curious if I'm using the gate driver in a way that would damage.

  • 0 in reply to Todd Petersen
    TI__Guru 54715 points

    OK, I think you have a high side N-ch switch array with VGATE 9V above one of the voltages.  The emitter-base of U7 is a diode, so if you have a 100k pull down on PACK, you have a voltage divider with the 100k and R82 which gives 1/11 of perhaps 35V or ~ 3.15V.

    I don't think you will hurt the device due to the large resistor used and since CHG can go to 60V (abs max).  However it may not provide the function you want.  A concern with a single transistor as drawn is that the transistor is always on since there is current flow in the E-B junction as long as VGATE is higher than CHG.  Also be aware that the C-B junction is also a PN junction.  Since battery+ and pack+ may be at different voltages, you may need a different VGATE for each, or a perhaps a zener limiter to keep the gate voltage in range of the FETs and your control circuit. For the control you need to take the CHG output which varies from PACK to PACK - 12V and provide an output range of SRC to SRC + 9V for the gates of your power FET array. I think there are various ways to make such a translator circuit, but I do not have a reference circuit.  The same consideration applies to DSG.

    Once you have a good control signal, consider if you need a push-pull circuit on the power FET gate(s). With the present schematic, the discharge FETs seem to be turned off by R3 and the charge FETs by R2.   Since discharge fault currents can often be large, the FETs may need to switch faster than the resistor alone can provide too keep the FETs in their safe operating area.  Charge currents are typically lower and may not need to switch off rapidly.

  • 0 in reply to WM5295
    Prodigy 60 points

    This is very helpful.    My team has been pouring over this problem and haven't had much luck on solving it.    Is there a reference circuit of the drive that you can provide?

    Todd

  • 0 in reply to Todd Petersen
    TI__Guru 54715 points

    No reference circuit like that.  As the circuit moves away from the standard one in the EVM they tend to get unique.  However the same switching topologies can often be re-used in different combinations.

    The switch for PACK from BAT controlled by your host uC might look similar to Q1 and Q2 from http://www.ti.com/lit/ug/sluu854/sluu854.pdf page 30.  You may want a N-ch FET from the host to pull PACK low.

    CHG could control a small signal P-ch FET from the PACK pin, much like the power FET but only providing a signal voltage on a resistor to ground.

    The charge power FET switch might be like Q15 from page 43 of http://www.ti.com/lit/ug/sluu474/sluu474.pdf with the 'driver' being like Q6, Q4 and related components.

    Of course you must re-calculate resistors for proper signal level and clamp gate voltages if needed.  I've not built this but it might be worth considering.

  • 0 in reply to WM5295
    Prodigy 60 points

    Thank you. 

    I think the main problem we're confused about is the drive circuit inside of the BQx.     We don't understand the equivalent circuit inside.    With our drive completely disconnected and VBAT at 30v the Pin 8 (DSG) is reporting 15v when active and 29.3 volts (one diode drop) when inactive.    Why would the driver not pull this completely to ground or at least one diode drop from ground?

  • 0 in reply to Todd Petersen
    TI__Guru 54715 points

    The DSG and CHG with respect to BAT and PACK pins.  The circuits are similar but independent.

    When part is ON and the output is ON, there is an internal regulator producing ~ 12V below the power pin.  The output (DSG or CHG) is connected to this regulated voltage through 1k ohm.  When the voltage gets too close to GND, the regulator will not be able to maintain the voltage and will limit at some low voltage near ground.  I don't know this voltage.

    When the part is ON and the output is OFF, it is clamped to the respective power pin with a low impedance switch, most likely a FET.

    The voltages for the above conditions are shown in the "FET Drive" section of the datasheet electrical tables.

    When the part is OFF, the driver is not powered. There is a 1M ohm resistor from the power pin to the output to help keep the external power FET off.  The internal clamp circuit has a parasitic FET from the output to the power pin, most likely the FET body diode.

    The CHG and DSG were implemented with regulated voltages to simplify connection to 20V Vgs power FETs.  In EVM testing transients were observed which made the zeners on the power FET gate attractive to avoid damage.to the power FETs.   Those zeners do not draw current continuously, they are only for transient protection.  If the part provided only open-drain type outputs which would pull to ground, there would be continuous current in the zeners and higher current in the system.